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Termination Options for
SSO Noise Analysis
The PlanAhead™ software has the ability to perform simultaneous switching noise (SSN)
analysis for each design, taking into account the actual I/O standards and options
assigned to the I/O pins in the target device and package. For details on how to use this
feature and perform the SSN analysis, see the "Using Noise Analysis Predictors" section of
UG632: PlanAhead User Guide.
For each output pin, there is the option to specify whether or not termination is present on
the board. The off-chip termination field automatically populates with the default
terminations for each I/O standard, if one exists.
Table A-1
the 7 series FPGAs when using the SSN predictor tool within the PlanAhead™ software.
For each I/O pin in the design, the user can specify whether to use these terminations, or
to have no termination.
Table A-1:
HSTL_I
HSTL_I_12
HSTL_I_18
HSTL_I_DCI
HSTL_I_DCI_18
HSTL_II
HSTL_II_18
HSTL_II_DCI
HSTL_II_DCI_18
HSTL_II_T_DCI
HSTL_II_T_DCI_18
HSUL_12
HSUL_12_DCI
LVCMOS (all voltages)
LVTTL (2 mA, 4 mA, 6 mA, and 8 mA drive)
7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
lists all of the default terminations for each of the I/O standards supported by
Default Terminations for SSN Noise Analysis by I/O Standard
(1)
IO Standard
www.xilinx.com
Appendix A
Default Termination
Far V
50Ω
TT
Far V
50Ω
TT
Far V
50Ω
TT
Far V
50Ω
TT
Far V
50Ω
TT
Near V
50Ω & Far V
50Ω
TT
TT
Near V
50Ω & Far V
50Ω
TT
TT
Far V
50Ω
TT
Far V
50Ω
TT
Far V
50Ω
TT
Far V
50Ω
TT
None
None
None
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