Rsds (Reduced Swing Differential Signaling); Mini-Lvds (Mini Low Voltage Differential Signaling) - Xilinx SelectIO 7 Series User Manual

Chapter 1: SelectIO Resources

RSDS (Reduced Swing Differential Signaling)

Table 1-45: Available I/O Bank Type
Reduced-swing differential signaling (RSDS) is similar to an LVDS high-speed interface
using differential signaling. RSDS has a similar implementation to LVDS_25 in 7 series
FPGAs and is only intended for point-to-point applications. RSDS is only available in HR
I/O banks and requires a V
RSDS_25.
supported.
Table 1-46: Allowed Attributes of the RSDS I/O Standard
IOSTANDARD
DIFF_TERM

Mini-LVDS (Mini Low Voltage Differential Signaling)

Table 1-47: Available I/O Bank Type
Mini-LVDS is a serial, intra-flat panel differential I/O standard that serves as an interface
between the timing control function and an LCD source driver. Mini-LVDS inputs require
a parallel-termination resistor, either by using a discrete resistor on the PCB, or by using
the 7 series FPGAs DIFF_TERM attribute to enable internal termination. Mini-LVDS is
only available in HR I/O banks and requires a V
IOSTANDARD is called MINI_LVDS_25.
Mini-LVDS I/O standards and attributes supported.
Table 1-48: Allowed Attributes of the Mini-LVDS I/O Standard
IOSTANDARD
DIFF_TERM
Notes:
1. When in bidirectional configuration, internal differential termination is always used for this
94
Send Feedback
HR
Available N/A
CCO
Table 1-46 summarizes all the possible RSDS I/O standards and attributes
Attributes
IBUFDS_DIFF_OUT, or
IBUFGDS_DIFF_OUT
HR HP
Available N/A
Attributes
IBUFDS_DIFF_OUT, or
IBUFGDS_DIFF_OUT
standard.
www.xilinx.com
HP
voltage level of 2.5V. The IOSTANDARD is called
Primitives
IBUFDS, IBUFGDS,
RSDS_25
TRUE, FALSE
voltage level of 2.5V. The
CCO
Table 1-48 summarizes all the possible
Primitives
IBUFDS, IBUFGDS,
MINI_LVDS_25
TRUE, FALSE
7 Series FPGAs SelectIO Resources User Guide
OBUFDS or OBUFTDS
N/A
(1)
OBUFDS or OBUFTDS
N/A
UG471 (v1.10) May 8, 2018