Lvdci (Low-Voltage Digitally Controlled Impedance) - Xilinx SelectIO 7 Series User Manual

Chapter 1: SelectIO Resources
Table 1-14
standard. This standard is available in both the HR and HP I/O banks.
Table 1-14: Allowed Attributes for the LVCMOS15 I/O Standard
IOSTANDARD
DRIVE
SLEW
Table 1-15
standard. This standard is available in both the HR and HP I/O banks.
Table 1-15: Allowed Attributes for the LVCMOS12 I/O Standard
IOSTANDARD
DRIVE
SLEW

LVDCI (Low-Voltage Digitally Controlled Impedance)

Table 1-16: Available I/O Bank Type
Using these I/O buffers configures the outputs as controlled impedance drivers. The
receiver of LVDCI is identical to a LVCMOS receiver. Some I/O standards, such as
LVCMOS, must have a drive impedance that matches the characteristic impedance of the
driven line. The HP I/O banks in the 7 series devices provide a controlled impedance
output driver to provide series termination without external-source termination resistors.
The impedance is set by the common external reference resistors, with resistance equal to
the trace characteristic impedance, Z
Sample circuits illustrating both unidirectional and bidirectional topologies for a
controlled impedance driver are shown in
standards supporting a controlled impedance driver are: LVDCI_15 and LVDCI_18.
56
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details the allowed attributes that can be applied to the LVCMOS15 I/O
Attributes
IBUF/IBUFG
LVCMOS15
details the allowed attributes that can be applied to the LVCMOS12 I/O
Attributes
IBUF/IBUFG
LVCMOS12
HR HP
N/A Available
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Primitives
OBUF/OBUFT/IOBUF
HP I/O Banks
LVCMOS15
N/A 2, 4, 6, 8, 12, 16
N/A {FAST, SLOW}
Primitives
OBUF/OBUFT/IOBUF
HP I/O Banks
LVCMOS12
N/A 2, 4, 6, 8
N/A {FAST, SLOW}
.
0
Figure 1-41 and Figure
7 Series FPGAs SelectIO Resources User Guide
HR I/O Banks
LVCMOS15
4, 8, 12, 16
{FAST, SLOW}
HR I/O Banks
LVCMOS12
4, 8, 12
{FAST, SLOW}
1-42. The DCI I/O
UG471 (v1.10) May 8, 2018