Table 2-9 Selection Of Baud Rate (When Dedicated Baud Rate Generate Used) - Fujitsu F2MC-8L Family series Hardware Manual

Peripherals
Table 2–9 Selection of Baud Rate (When Dedicated Baud Rate Generate Used)
RC2 RC1 RC0 Division
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
HARDWARE CONFIGURATION
ratio
4.9152 MHz
1/4
1/64
0
2 9600
1
2 4800
2
2 2400
3
2 1200
4
2 600
5
2 300
6
2 150
7
2 75
(e) Selection of input/output signal
The UART shares the data and clock input/output with the serial I/O.
Therefore, the output signal selected by the RSEL bit is output. At switching
between port output and peripheral output, the peripheral enable bit
selected by the RSEL bit becomes valid.
• When the RSEL bit is 0, UART is selected.
• When the RSEL bit is 1, serial I/O is selected.
(5) Precautions for UART
• After canceling register initialization by reset, 11 shift clocks are required
to initialize the internal control section.
• When using the external clock, the minimum pulse width is as follows:
CPU operating clock cycle × 4
Baud rate (bps)
5 MHz
1/4 1/65
1/8 1/16
78125 2404
39063 1202
19531 601
9766 300
4883 150
2441 75
1221 38
610 19
2– 49
Remarks
Clock
PDS division
CS,CR division