Table of Contents
Advertisement
MC68302 Applications
D.5.8 Final Notes
Only three signals, DREQ, DACK, and DONE, are used to control the handshake between
the peripheral and the IDMA. DONE is not needed unless the number of bytes to transmit is
not known. The DACK signal can select the peripheral device when data is being transferred
to or from it, and wait-state logic can generate DTACK to indicate when valid data is on the
bus. Software controls data transfer by setting bits in the CMR as shown in Table D-2 and
loading the SAPR and DAPR. It then waits for completion of the transfer by either monitoring
the bits in the CSR (see Table D-3) or by using interrupt processing.
D.6 MC68302 MULTIPROTOCOL CONTROLLER TIED TO IDL BUS FORMS
AND ISDN VOICE/DATA TERMINAL
The following paragraphs discuss how the MC68302 can be tied to the interchip digital link
(IDL) bus, which enables connectivity to a family of ISDN chips. The IDL bus connects the
MC68302 integrated controller with the MC145475 S/T interface and the MC145554 CO-
DEC to form a basic rate ISDN voice/data terminal (see Figure D-11).
The MC68302 is the first device to combine the benefits of the M68000 microprocessor with
a flexible communications architecture. This CMOS device incorporates an MC68000 or
MC68008 core processor, a communications RISC processor with associated peripherals,
and a system integration block.
EPROM
RAM
D-30
SCP
MC68302
SCC1
IMP
SCC3
SCC2
NON-ISDN
TERMINAL
ISDN VOICE/DATA TERMINAL
Figure D-11. ISDN Voice/Data Terminal
MC68302 USER'S MANUAL
SCP BUS
IDL BUS
STROBE
MC145554
CODEC
HANDSET
S/T
LOOP
MC145475
S/T
INTERFACE
MOTOROLA
Advertisement
Table of Contents
