Specifications; Rf And Pll Specifications - Analog Devices ADF7021-V Manual

ADF7021-V

SPECIFICATIONS

V = 2.3 V to 3.6 V, GND = 0 V, T
DD
measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version
number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth.

RF AND PLL SPECIFICATIONS

Table 1.
Parameter
RF CHARACTERISTICS
Phase Frequency Detector (PFD)
Frequency
PHASE-LOCKED LOOP (PLL)
Normalized In-Band Phase Noise
1
Floor
PLL Settling
EXTERNAL VCO
Tuning Range
Pin L2 Input Sensitivity
REFERENCE INPUT
2
Crystal Reference
2, 3
External Oscillator
4
Crystal Start-Up Time
XTAL Bias = 20 μA
XTAL Bias = 35 μA
Input Level for External Oscillator
OSC1 Pin
OSC2 Pin
ADC PARAMETERS
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1
This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance
as seen at the power amplifier (PA) output: −203 + 10 log(f
2
Guaranteed by design. Sample tested to ensure compliance.
3
A TCXO, VCXO, or OCXO can be used as an external oscillator.
4 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.
= T to T , unless otherwise noted. Typical specifications are at V
A MIN MAX
Min Typ
RF/256
−203
155
0.2
0
3.625
3.625
0.930
0.438
0.8
CMOS levels
±0.4
±0.4
) + 20 logN.
PFD
Rev. 0 | Page 4 of 60
Max Unit Test Conditions/Comments
24 MHz
Maximum usable PFD at a particular RF frequency
is limited by the minimum N divider value
dBc/Hz
μs Measured for a 100 kHz frequency step to within
5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz
2 V
dBm VCO frequency < 1920 MHz
24 MHz
24 MHz
10 MHz XTAL, 33 pF load capacitors, V
ms
ms
V p-p Clipped sine wave
V
V = 2.3 V to 3.6 V, T
DD
LSB
LSB
= 3 V, T = 25°C. All
DD A
= 3.0 V
DD
= 25°C
A