Saving Registers - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupt

5.3.3 Saving Registers

In an interrupt sequence, the FLG register and the PC are saved to the stack area.
The order in which these contents are saved is as follows: First, the 4 high-order bits of the PC and 4
high-order bits (IPL) and 8 low-order bits of the FLG register for a total of 16 bits are saved to the stack
area. Next, the 16 low-order bits of the PC are saved. Figure 5.3.3 shows the stack status before an
interrupt request is acknowledged.
If there are any other registers you want to be saved, save them in program at the beginning of the
interrupt routine. The PUSHM instruction allows you to save all registers except the SP by a single
instruction.
S t a c k a r e a
M S B
A d d r e s s
m – 4
m – 3
m – 2
m – 1
m Content of previous stack
Content of previous stack
m + 1
Stack status before interrupt request is
acknowledged
Figure 5.3.3 Stack status before and after an interrupt request is acknowledged
Register save operation performed in an interrupt sequence is executed in four operations 8 bits at a time.
Figure 5.3.4 shows the operation to save registers.
Note 1: When the INT instruction for software interrupt numbers 32 to 63 is executed, SP is indicated by
the U flag. The others are ISP.
Figure 5.3.4 Operations to save registers
LSB
[ S P ]
S P v a l u e b e f o r e
i n t e r r u p t r e q u e s t i s
a c k n o w l e d g e d
A d d r e s s Stack area
[ S P ] – 5
[ S P ] – 4
PC
[ S P ] – 3 P C
[ S P ] – 2 FLG
[ S P ] – 1
F L G H
[SP]
N o t e 1 : [ S P ] d e n o t e s t h e i n i t i a l v a l u e o f t h e s t a c k p o i n t e r ( S P ) w h e n
i n t e r r u p t r e q u e s t i s a c k n o w l e d g e d . A f t e r t h e m i c r o c o m p u t e r
f i n i s h e s s a v i n g r e g i s t e r s , t h e S P c o n t e n t i s [ S P ] m i n u s 4 .
Stack area
MSB
Address
m – 4
m – 3
m – 2
m – 1
F L G H
m Content of previous stack
C o n t e n t o f p r e v i o u s s t a c k
m + 1
Stack status after interrupt request is acknowledged
Sequence in which order
registers are saved
( 3 )
L
M
( 4 )
Saved separately, 8 bits at a time
L
( 1 )
P C
( 2 )
H
F i n i s h e d s a v i n g r e g i s t e r s
i n f o u r o p e r a t i o n s .
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5.3 Interrupt Sequence
L S B
[ S P ]
PC
N e w S P v a l u e
L
PC
M
FLG
L
P C
H