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NEC VR4131 mPD30131 Preliminary User's Manual

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Preliminary User's Manual

V

4131™

R

64/32-Bit Microprocessor

Hardware

µ µ µ µ PD30131

Document No. U15350EJ2V0UM00 (2nd edition)

Date Published March 2002 N CP(K)

©

2002

2000

Printed in Japan

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Page 1 Preliminary User’s Manual 4131™ 64/32-Bit Microprocessor Hardware µ µ µ µ PD30131 Document No. U15350EJ2V0UM00 (2nd edition) Date Published March 2002 N CP(K) © 2002 2000 Printed in Japan...
Page 2 [MEMO] Preliminary User’s Manual U15350EJ2V0UM...
Page 3 4131, V 4400, and V 4173 are trademarks of NEC Corporation. MIPS is a registered trademark of MIPS Technologies, Inc. in the United States. iAPX is a trademark of Intel Corporation. DEC VAX is a trademark of Digital Equipment Corporation.
Page 4 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 PREFACE Readers This manual is intended for users who wish to gain an understanding of the functions of the V 4131 in order to design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the hardware of the 4131 described in the Organization below.
Page 7 Related Documents When using this manual, also read the following documents. The related documents indicated in this publication may include preliminary versions. However preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 4131 Hardware User's Manual This Manual µ...
Page 8: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION......................... 24 1.1 Features............................24 1.2 Ordering Information......................... 25 1.3 64-Bit Architecture ........................25 1.4 V 4131 Processor ........................25 1.4.1 Internal block structure ........................26 1.4.2 I/O registers............................. 28 1.5 V 4130 CPU Core........................36 1.5.1 Internal block configuration ......................
Page 9 3.1.1 ROM address space ........................76 3.1.2 PCI bus address space ........................80 3.1.3 DMA ..............................80 3.1.4 Internal I/O space..........................82 3.1.5 External I/O address space......................83 3.1.6 DRAM address space ........................83 CHAPTER 4 EXCEPTION PROCESSING ....................86 4.1 Overview of Exceptions......................86 4.1.1 Exception operation .........................86 4.1.2 Exception vector address.........................86 4.1.3...
Page 10 6.3.1 Cold reset ............................127 6.3.2 Soft reset ............................129 6.4 V 4131 Processor Modes ...................... 130 6.4.1 Power modes..........................130 6.4.2 Privilege mode..........................131 6.4.3 Reverse endian ..........................131 6.4.4 Bootstrap exception vector (BEV) ....................132 6.4.5 Cache error check ......................... 132 6.4.6 Parity error disable ........................
Page 11 8.2.6 FIR DMA address registers ......................168 8.2.7 DMA base address register for RAM space ...................169 8.2.8 DMA address register for RAM space....................170 8.2.9 DMA base address register for I/O space ..................171 8.2.10 DMA address register for I/O space ....................172 CHAPTER 9 DCU (DMA CONTROL UNIT) ..................173 9.1 General ............................173 9.2 DMA Priority Control.......................173 9.3 Register Set ..........................173...
Page 12 11.2.16 SCUINTREG (0x0F00 00AE) ...................... 206 11.2.17 CSIINTREG (0x0F00 00B0) ......................207 11.2.18 MPCIINTREG (0x0F00 00B2) ..................... 208 11.2.19 MSCUINTREG (0x0F00 00B4)....................209 11.2.20 MCSIINTREG (0x0F00 00B6) ..................... 210 11.2.21 BCUINTREG (0x0F00 00B8)....................... 211 11.2.22 MBCUINTREG (0x0F00 00BA) ....................212 11.3 Notes for Register Setting ....................
Page 13 14.2.8 GIUINTENH (0x0F00 014E)......................264 14.2.9 GIUINTTYPL (0x0F00 0150)......................265 14.2.10 GIUINTTYPH (0x0F00 0152) .......................266 14.2.11 GIUINTALSELL (0x0F00 0154) ....................267 14.2.12 GIUINTALSELH (0x0F00 0156) ....................268 14.2.13 GIUINTHTSELL (0x0F00 0158) ....................269 14.2.14 GIUINTHTSELH (0x0F00 015A) ....................270 14.2.15 GIUPODATEN (0x0F00 015C).....................272 14.2.16 GIUPODATL (0x0F00 015E)......................273 CHAPTER 15 SCU (SysAD CONTROL UNIT) ...................274 15.1 Outline ............................274 15.2 Register Set ..........................274...
Page 14 17.7.1 Address conversion........................302 17.7.2 Command conversion........................302 17.7.3 Delayed transaction........................303 17.7.4 Posted transaction......................... 303 17.7.5 Precautions ........................... 303 17.8 Interrupts........................... 304 17.9 Internal Register Set....................... 305 17.9.1 PCIMMAW1REG (0x0F00 0C00) ....................306 17.9.2 PCIMMAW2REG (0x0F00 0C04) ....................307 17.9.3 PCITAW1REG (0x0F00 0C08)......................
Page 15 18.2.5 DSIUDLM (0x0F00 0821: LCR7 = 1)....................346 18.2.6 DSIUIID (0x0F00 0822: Read) .......................347 18.2.7 DSIUFC (0x0F00 0822: Write) .......................349 18.2.8 DSIULC (0x0F00 0823)........................352 18.2.9 DSIUMC (0x0F00 0824).........................353 18.2.10 DSIULS (0x0F00 0825)........................354 18.2.11 DSIUMS (0x0F00 0826).......................356 18.2.12 DSIUSC (0x0F00 0827) .......................357 18.2.13 SIURESET (0x0F00 0809)......................357 CHAPTER 19 LED (LED CONTROL UNIT) ..................358 19.1 General ............................358...
Page 16 21.2.6 CSI_SOTBFREG (0x0F00 01A8) ....................389 21.2.7 CSI_SIOREG (0x0F00 01AA) ....................... 390 21.2.8 CSI_CNTREG (0x0F00 01B0)....................... 391 21.2.9 CSI_INTREG (0x0F00 01B2) ......................393 21.2.10 CSI_IFIFOVREG (0x0F00 01B4) ....................395 21.2.11 CSI_OFIFOVREG (0x0F00 01B6)....................397 21.2.12 CSI_IFIFOREG (0x0F00 01B8)....................399 21.2.13 CSI_OFIFOREG (0x0F00 01BA)....................400 21.2.14 CSI_FIFOTRGREG (0x0F00 01BC)....................
Page 17 A.1 Changes in Pin Functions .....................439 A.1.1 Pin Functions ..........................439 A.1.2 Pin Status............................441 A.2 Functions Added to/Deleted from Revision 2.0 ..............442 A.2.1 Addition of N-Wire interface function....................442 A.2.2 Elimination of MMU disable mode....................443 A.3 Functions Added to Revision 2.1 ..................444 A.3.1 Addition of PCIU internal register....................444 APPENDIX B INDEX..........................447 Preliminary User’s Manual U15350EJ2V0UM...
Page 18 LIST OF FIGURES (1/3) Figure No. Title Page 4131 Internal Block Diagram and Example of Connection to External Blocks......... 26 4130 CPU Core Internal Block Diagram ....................36 4131 CPU Registers ..........................38 CPU Instruction Formats (32-Bit Length Instruction) ................... 38 CPU Instruction Formats (16-bit length instruction) ..................
Page 19 LIST OF FIGURES (2/3) Figure No. Title Page 5-23 PErr Register Format ..........................114 5-24 CacheErr Register Format ..........................114 5-25 TagLo Register ............................115 5-26 TagHi Register............................115 5-27 ErrorEPC Register Format (When MIPS16ISA Is Disabled)...............117 5-28 ErrorEPC Register Format (When MIPS16ISA Is Enabled)................117 RTC Reset ..............................119 Power Supply Control Timing When Using SDRAM ...................121 RSTSW ...............................122...
Page 20 LIST OF FIGURES (3/3) Figure No. Title Page 12-4 Activation via GPIO Activation Interrupt (BATTINH/BATTINT# = 0) ............218 12-5 Activation via DCD Interrupt (BATTINH/BATTINT# = 1) ................219 12-6 Activation via DCD Interrupt (BATTINH/BATTINT# = 0) ................219 12-7 Activation via Elapsed Timer Interrupt (BATTINH/BATTINT# = 1).............
Page 21 LIST OF TABLES (1/3) Table No. Title Page BCU Registers ..............................28 DMAAU Registers............................28 DCU Registers ..............................29 CMU Register ...............................29 ICU Registers ...............................29 PMU Registers..............................30 RTC Registers ..............................30 GIU Registers ...............................31 SCU Registers ..............................31 1-10 SDRAMU Registers ............................31 1-11 PCI Internal Registers...........................32 1-12 PCI Configuration Header Registers......................32 1-13...
Page 22 LIST OF TABLES (2/3) Table No. Title Page Internal I/O Space 1 ............................. 82 External I/O Space ............................83 DRAM Address Example (When Using 16-Bit Data Bus) ................84 DRAM Address Example When Using 16 Mb Expansion DRAM (When Using 32-Bit Data Bus)....85 64-Bit Mode Exception Vector Base Addresses ..................
Page 23 LIST OF TABLES (3/3) Table No. Title Page 14-1 GPIO Pins ..............................255 14-2 GIU Registers .............................256 14-3 Correspondence Between Interrupt Mask and Interrupt Hold..............271 14-4 Correspondence Between GPIO(35:32) and Alternate Function Pins............272 15-1 SCU Registers ............................274 15-2 Notification of Illegal Access ........................279 16-1 SDRAM Registers............................280 16-2...
Page 24: Chapter 1 Introduction
4131, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS , is one of the RISC microprocessor V Series products manufactured by NEC. The V 4131 accommodates the ultra low power consumption V...
Page 25: Ordering Information
CHAPTER 1 INTRODUCTION Effective power management features, which include the following five operating modes: • Fullspeed mode: Normal operating mode in which all clocks operate • Standby mode: All internal clocks stop except for timer or interrupt-related clocks • Suspend mode: Bus clock and all internal clocks stop except for timer or interrupt-related clocks •...
Page 26: Internal Block Structure
CHAPTER 1 INTRODUCTION Figure 1-1. V 4131 Internal Block Diagram and Example of Connection to External Blocks 32.768 kHz 18.432 MHz 4173 PCI bus Touch panel 4130 CPU core PC card LCDC LCD panel PCIU DSIU SDRAM SDRAMU DMAAU RS-232-C driver ROM/ Flash memory...
Page 27 CHAPTER 1 INTRODUCTION (5) Direct memory access address unit (DMAAU) The DMAAU controls the address of the following three different DMA transfers. • DMA between PCI bus and memory bus • DMA between on-chip CPU I/O and memory bus • DMA between general-purpose I/O device and memory (6) Direct memory access control unit (DCU) The DCU controls the arbitration of three different DMA transfers.
Page 28: I/O Registers
CHAPTER 1 INTRODUCTION 1.4.2 I/O registers The I/O registers are used for peripheral unit control. Lists of registers for peripheral units are as follows. Table 1-1. BCU Registers Register Symbol Function Physical Address BCUCNTREG1 BCU control register 1 0x0F00 0000 ROMSIZEREG ROM size register 0x0F00 0004...
Page 29 CHAPTER 1 INTRODUCTION Table 1-3. DCU Registers Register Symbol Function Physical Address DMARSTREG DMA reset register 0x0B00 0040 DMAIDLEREG DMA sequencer status register 0x0B00 0042 DMASENREG DMA sequencer enable register 0x0B00 0044 DMAMSKREG DMA mask register 0x0B00 0046 DMAREQREG DMA request register 0x0B00 0048 TDREG Transfer direction setting register...
Page 30 CHAPTER 1 INTRODUCTION Table 1-6. PMU Registers Register Symbol Function Physical Address PMUINTREG PMU interrupt/status register 0x0F00 00C0 PMUCNTREG PMU control register 0x0F00 00C2 PMUINT2REG PMU interrupt/status register 2 0x0F00 00C4 PMUCNT2REG PMU control register 2 0x0F00 00C6 PMUWAITREG PMU wait count register 0x0F00 00C8 PMUCLKDIVREG PMU Div mode register...
Page 31 CHAPTER 1 INTRODUCTION Table 1-8. GIU Registers Register Symbol Function Physical Address GIUIOSELL GPIO input/output select lower register 0x0F00 0140 GIUIOSELH GPIO input/output select higher register 0x0F00 0142 GIUPIODL GPIO port input/output data lower register 0x0F00 0144 GIUPIODH GPIO port input/output data higher register 0x0F00 0146 GIUINTSTATL GPIO interrupt status lower register...
Page 32 CHAPTER 1 INTRODUCTION Table 1-11. PCI Internal Registers Register Symbol Function Physical Address PCIMMAW1REG Master transaction PCI memory space address conversion register 1 0x0F00 0C00 PCIMMAW2REG Master transaction PCI memory space address conversion register 2 0x0F00 0C04 PCITAW1REG Target transaction internal memory space conversion register 1 0x0F00 0C08 PCITAW2REG Target transaction internal memory space conversion register 2...
Page 33 CHAPTER 1 INTRODUCTION Table 1-13. DSIU Registers Register Symbol Function LCR7 Bit Physical Address DSIURB Receive buffer register (read) 0x0F00 0820 DSIUTH Transmission hold register (write) DSIUDLL Division ratio lower register DSIUIE Interrupt enable register 0x0F00 0821 DSIUDLM Division ratio higher register ...
Page 34 CHAPTER 1 INTRODUCTION Table 1-15. SIU Registers Register Symbol Function LCR 7 Physical Address SIURB Receive buffer register (read) 0x0F00 0800 SIUTH Transmission hold register (write) SIUDLL Division ratio lower register SIUIE Interrupt enable register 0x0F00 0801 SIUDLM Division ratio higher register −...
Page 35 CHAPTER 1 INTRODUCTION Table 1-17. FIR Registers Register Symbol Function Physical Address FRSTR FIR reset register 0x0F00 0840 DPINTR DMA page interrupt register 0x0F00 0842 DPCNTR DMA page control register 0x0F00 0844 Transmit data register 0x0F00 0850 Receive data register 0x0F00 0852 Interrupt mask register 0x0F00 0854...
Page 36: R 4130 Cpu Core
CHAPTER 1 INTRODUCTION 1.5 V 4130 CPU Core Figure 1-2 shows the internal block diagram of the V 4130 CPU core. The V 4130 core employs 2-way superscalar architecture. In addition to the conventional high-performance integer operation units, this CPU core has a full-associative format translation lookaside buffer (TLB), which has 32 entries that provide mapping to 2-page pairs for one entry.
Page 37: Cpu Registers
CHAPTER 1 INTRODUCTION (5) Bus interface The bus interface controls data transmission/reception between the V 4130 CPU core and the BCU, which is one of the peripheral units. The bus interface consists of two 32-bit multiplexed address/data buses (one for input, and the other for output), clock signals, interrupt request signals, and various other control signals.
Page 38: Cpu Instruction Set Overview
CHAPTER 1 INTRODUCTION Figure 1-3. V 4131 CPU Registers General-purpose registers Multiply/divide registers r0 = 0 Program counter r31 = LinkAddress The V 4131 has no program status word (PSW) register as such; this is covered by the status and cause registers incorporated within the system control coprocessor (CP0).
Page 39 CHAPTER 1 INTRODUCTION The instruction set can be further divided into the following five groupings: (a) Load and store instructions move data between the memory and the general-purpose registers. They are all immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed immediate offset.
Page 40 CHAPTER 1 INTRODUCTION Figure 1-5. CPU Instruction Formats (16-bit length instruction) I type Immediate RI type Immediate RR type funct RRI type Immediate RRR type RRI-A type RRI-A Immediate Shift type SHIFT Shamt I8 type funct Immediate I8_MOVR32 type funct r32[4:0] I8_MOV32R type funct...
Page 41: Data Formats And Addressing
CHAPTER 1 INTRODUCTION The instruction set can be further divided into the following four groupings: (a) Load and store instructions move data between memory and general-purpose registers. They include RRI, RI, I8, and RI64 types. (b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in registers.
Page 42 CHAPTER 1 INTRODUCTION Figure 1-6. Little-Endian Byte Ordering in Word Data (a) Litlle endian Bit No. Higher Word address address Lower address (b) Big endian Bit No. Higher Word address address Lower address Remarks 1. The lowest byte is the lowest address. 2.
Page 43 CHAPTER 1 INTRODUCTION Figure 1-7. Little-Endian Byte Ordering in Doubleword Data (a) Litlle endian Word Halfword Byte Higher Doubleword address address 16 15 Lower address (b) Big endian Word Halfword Byte Higher Doubleword address address 16 15 Lower address Remarks 1. The lowest byte is the lowest address. 2.
Page 44: System Control Coprocessor (Cp0)
CHAPTER 1 INTRODUCTION The V 4130 CPU core uses the following byte boundaries for halfword, word, and doubleword accesses: • Halfword: An even byte boundary (0, 2, 4...) • Word: A byte boundary divisible by four (0, 4, 8...) • Doubleword: A byte boundary divisible by eight (0, 8, 16...) The following special instructions are used to load and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundaries: These instructions are used in pairs to provide access to misaligned data.
Page 45 CHAPTER 1 INTRODUCTION Figure 1-9. CP0 Registers Register No. Register name Register No. Register name Note 1 Note 1 Index Config Note 1 Note 1 Random LLAddr Note 1 Note 2 EntryLo0 WatchLo Note 1 Note 2 EntryLo1 WatchHi Note 2 Note 2 Context XContext...
Page 46 CHAPTER 1 INTRODUCTION Table 1-18. System Control Coprocessor (CP0) Register Definitions Register Number Register Name Description Index Programmable pointer to TLB array Random Pseudo-random pointer to TLB array (read only) EntryLo0 Lower side of TLB entry for even PFN EntryLo1 Lower side of TLB entry for odd PFN Context Pointer to kernel virtual PTE in 32-bit mode...
Page 47: Floating-Point Unit (Fpu)
CHAPTER 1 INTRODUCTION 1.5.6 Floating-point unit (FPU) The V 4131 does not support the floating-point unit (FPU). A coprocessor unusable exception will occur if any FPU instructions are executed. If necessary, FPU instructions should be emulated by software in an exception handler.
Page 48: Operating Modes
CHAPTER 1 INTRODUCTION 1.6.2 Operating modes The V 4122 has the following three operating modes: • User mode • Supervisor mode • Kernel mode The manner in which memory addresses are translated or mapped depends on these operating modes. Refer to CHAPTER 3 MEMORY MANAGEMENT SYSTEM for details.
Page 49 CHAPTER 1 INTRODUCTION • • • • PCICLK (output) PCICLK supplies the controller on the PCI bus with the clock. The initial value is 1/2 the VTClock frequency. The PCICLK output can be changed by setting PCICLKSELREG. • • • • VTClock (internal) This is the reference clock of the ROM, I/O, and SDRAM access.
Page 50 CHAPTER 1 INTRODUCTION Table 1-19. CLKSEL Pin Setting and Frequency of Each Clock Note 1 Note 2 CLKSEL(2:0) PClock VTClock PCICLK (At 1/2 of VTClock) MIN. MAX. 199.1 MHz 33.2 MHz 99.5 MHz 49.75 MHz 181.0 MHz 30.2 MHz 90.5 MHz 45.25 MHz 165.9 MHz 27.6 MHz...
Page 51 CHAPTER 1 INTRODUCTION Figure 1-10 shows the external circuits of the clock oscillator. Figure 1-10. External Circuits of Clock Oscillator (a) Crystal oscillation (b) External clock 4131 4131 External Note 1 clock Note 1 Open Note 2 Note 2 Notes 1. CLKX1, RTCX1 2.
Page 52 CHAPTER 1 INTRODUCTION Figure 1-11. Incorrect Connection Circuits of Resonator (a) Connection circuit wiring is too long. (b) There is another signal line crossing. Note 1 Note 2 Note 1 Note 2 (c) A high fluctuating current flows near a signal line. (d) A current flows over the ground line of the oscillator (The potentials of points A, B, and C change).
Page 53: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS Caution CHAPTER2 describes revision 1.2 or earlier. When using revision 2.0 or later, also read APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER. 2.1 Pin Configuration • 224-pin plastic FBGA (16 × 16 mm) Top View Bottom View T R P N M L K J H G F E D C B A...
Page 54 CHAPTER 2 PIN FUNCTIONS Power Power Power Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Supply Supply Supply 3.3 V CLKOUT 3.3 V 3.3 V ADD13 1.5 V 3.3 V CBE2 3.3 V DATA5 1.5 V 3.3 V DEVSEL# 3.3 V...
Page 55 CHAPTER 2 PIN FUNCTIONS Power Power Power Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Supply Supply Supply 3.3 V GND3 3.3 V DATA27/GPIO27 1.5 V GND1 3.3 V RTS#/CLKSEL1 3.3 V DATA31/GPIO31 3.3 V 3.3 V DCTS#/GPIO35 3.3 V 3.3 V...
Page 56 CHAPTER 2 PIN FUNCTIONS Pin Identification AD(0:31): Address/data bus IRDY#: Initiator ready ADD(1:24): Address bus IRDIN: IrDA data input BATTINH: Battery inhibit IRDOUT#: IrDA data output BATTINT#: Battery interrupt request LEDOUT#: LED output BIGENDIAN: Big endian LOCK#: Lock CAS: Column address strobe MIPS16EN: MIPS16 enable CBE(0:3):...
Page 57: Pin Function Description
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Function Description The functional classifications of the V 4131 pins are listed below. Remark # indicates active low. Figure 2-1. V 4131 Signal Classification ADD(1:24) TxD/CLKSEL2 DATA(0:15) RTS#/CLKSEL1 DATA(16:31)/GPIO(16:31) RS-232-C DTR#/CLKSEL0 CKE(0:1) interface CTS# DQM(0:3) DCD#/GPIO15 CS(0:1)#...
Page 58: Memory Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.1 Memory interface signals The memory interface signals are used to connect the V 4131 with SDRAM and ROM in the system. Table 2-1. Memory Interface Signals (1/2) Signal Function SCLK Output Operation clock for SDRAM ADD(1:24) Output Higher 24 bits of the 25-bit address bus These signals are used to specify addresses for the V...
Page 59: I/O Device Interface Signals
CHAPTER 2 PIN FUNCTIONS Table 2-1. Memory Interface Signals (2/2) Signal Function DQM0 Output The function differs depending on the connected device. When SDRAM is accessed: This is the byte enable signal for DATA(0:7). When a 32-bit external I/O device is accessed: This is the byte enable signal for DATA(0:7). When a 16-bit external I/O device is accessed: This is the high-byte enable signal of the I/O bus.
Page 60: Clock Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.3 Clock interface signals These signals are used to supply clocks. Table 2-3. Clock Interface Signals Signal Function RTCX1 Input This is the 32.768 kHz oscillator’s input pin. It is connected to one side of a crystal resonator. RTCX2 Output This is the 32.768 kHz oscillator’s output pin.
Page 61: Rs-232C Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.6 RS-232C interface signals The RS-232C interface signals control the transmission of data between the RS-232C controller and the V 4131. The RS-232C function and the IrDA function are not used together. These signals have alternate functions as the initialization setting signals set after RTC reset.
Page 62: Debug Serial Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.7 Debug serial interface signals The debug serial interface signals control the transmission of the debug serial data of the V 4131. Some signals have alternate functions as the initialization setting signals set after RTC reset. Table 2-8.
Page 63: Clocked Serial Signals
CHAPTER 2 PIN FUNCTIONS 2.2.9 Clocked serial signals The clocked serial signals are 3-wire clocked serial signals of the V 4131. Table 2-10. Clocked Serial Signals Signal Function Input Clocked serial input signal SOUT Output Clocked serial output signal SECLK Output Synchronous clock output for the clocked serial 2.2.10 General-purpose I/O signals These are general-purpose I/O pins of the V...
Page 64: Pci Like Bus Interface Signals
CHAPTER 2 PIN FUNCTIONS 2.2.12 PCI Like bus interface signals These are the signals that comply with the V 4131 PCI bus. This PCI Like bus interface is compliant with PCI revision 2.1, thus allowing connection of up to three master PCI devices. Table 2-13.
Page 65: Dedicated V Dd And Gnd Signals
CHAPTER 2 PIN FUNCTIONS 2.2.13 Dedicated V and GND signals Table 2-14. Dedicated V and GND Signals Signal Name Power Supply Function 1.5 V Dedicated V for the PLL analog unit GNDP 1.5 V Dedicated GND for the PLL analog unit 1.5 V Dedicated V for the PLL digital unit.
Page 66: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Status 2.3.1 Pin status in specific states Table 2-16 lists the pin status after the V 4131 is reset or when it is in the power mode. Table 2-16. Pin Status in Specific States (1/4) Pin Name When Reset by In Hibernate Mode or...
Page 67 CHAPTER 2 PIN FUNCTIONS Table 2-16. Pin Status upon Specific States (2/4) Pin Name When Reset In Hibernate Mode or When Reset by In Suspend Mode During Bus Hold by RTCRST During HALTimer RSTSW Shutdown DATA(31:16)/GPIO(31:16) Note 1 Note 1 Note 1 Note 2 Note 3...
Page 68 CHAPTER 2 PIN FUNCTIONS Table 2-16. Pin Status upon Specific States (3/4) Pin Name When Reset by In Hibernate Mode or When Reset by In Suspend During Bus RTCRST During HALTimer RSTSW Mode Hold Shutdown GNT(2:0)# Hi-Z Hi-Z Hi-Z Hold Hold GPIO(5:0) Hi-Z...
Page 69 CHAPTER 2 PIN FUNCTIONS Table 2-16. Pin Status upon Specific States (4/4) Pin Name When Reset by In Hibernate Mode or When Reset by In Suspend During Bus RTCRST During HALTimer RSTSW Mode Hold Shutdown RTS#/CLKSEL1 Hi-Z Hold Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z...
Page 70: Pin Handling And I/O Circuit Types
CHAPTER 2 PIN FUNCTIONS 2.3.2 Pin Handling and I/O Circuit Types Table 2-17. Pin Handling and I/O Circuit Types (1/2) Pin Name Pin Handling Recommended Connection of Unused Drive I/O Circuit Pins Capability Type − − AD(31:0) Leave open − −...
Page 71 CHAPTER 2 PIN FUNCTIONS Remarks 1. No external processing is required for the pins for which no instruction is described (−) in the Pin Handling column. 2. For pins for which any instruction is specified in the Recommended Connection of Unused Pins column (−), follow the instruction provided in the Pin Handling column.
Page 72 CHAPTER 2 PIN FUNCTIONS Table 2-17. Pin Handling and I/O Circuit Types (2/2) Pin Name Pin Handling Recommended Connection of Unused Drive I/O Circuit Pins Capability Type − − IORDY Connect V or GND via a resistor − − IRDIN Connect V or GND via a resistor −...
Page 73: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS Remarks 1. No external processing is required for the pins to which no instruction is described (−) in the Pin Handling column. 2. For pins for which no instruction is specified in the Recommended Connection of Unused Pins column (−), follow the instruction provided in the Pin Handling column.
Page 74: Chapter 3 Memory Management System
CHAPTER 3 MEMORY MANAGEMENT SYSTEM The V 4131 provides a memory management unit (MMU) that uses a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. This chapter describes the physical addresses. For the operation of the TLB and the memory mapping method used to translate virtual addresses into physical addresses, refer to the V 4100 Series Architecture User's Manual available separately.
Page 75: Physical Address Space
CHAPTER 3 MEMORY MANAGEMENT SYSTEM 3.1 Physical Address Space Because the V 4130 core uses a 32-bit address, the processor physical address space encompasses 4 GB. The 4131 uses this 4 GB physical address space as shown in Figure 3-1. Figure 3-1.
Page 76: Rom Address Space
CHAPTER 3 MEMORY MANAGEMENT SYSTEM Table 3-1. V 4131 Physical Address Space Physical Address Space Capacity (Bytes) 0xFFFF FFFF to 0x2000 0000 Mirror image of 0x1FFF FFFF to 0x0000 0000 3.5 G 0x1FFF FFFF to 0x1800 0000 ROM space 128 M 0x17FF FFFF to 0x1000 0000 PCI space 128 M...
Page 77 CHAPTER 3 MEMORY MANAGEMENT SYSTEM (2) Mapping of physical address The area for each bank is determined based on the data bus bit width and the bank capacity, as described below. (a) In 16-bit bus mode (DBUS32 = 0) Bank 3 (CS3#/ROMCS3#): 0x1FFF FFFF to 0x1FFF FFFF − (Bank 3 capacity) Bank 2 (CS2#/ROMCS2#): 0x1FFF FFFF −...
Page 78 CHAPTER 3 MEMORY MANAGEMENT SYSTEM (b) In 32-bit bus mode (DBUS32 = 1) Bank 1 (ROMCS1#): 0x1FFF FFFF to 0x1FFF FFFF − (Bank 1 capacity) Bank 0 (ROMCS0#): 0x1FFF FFFF − (Bank 1 capacity + 1 byte) to 0x1FFF FFFF − (Bank 1 capacity + Bank 0 capacity) Bank 3 (CS3#/ROMCS3#): 0x1FFF FFFF −...
Page 79 CHAPTER 3 MEMORY MANAGEMENT SYSTEM Physical addresses in the ROM address space are indicated in the following table when using 64 Mb ROM (banks 3 and 2), or 32 Mb or 64 Mb ROM (bank 1 and 0). Table 3-4. Example of ROM Addresses When Using 64 Mb Expansion ROM (When Using 32-Bit Data Bus) Note 1 Physical Address ADD(24:1) Pin...
Page 80: Pci Bus Address Space
CHAPTER 3 MEMORY MANAGEMENT SYSTEM 3.1.2 PCI bus address space The V 4131 has an internal I/O space. The following tables show each address space. • PCI bus I/O space This corresponds to the PCI I/O space. • PCI bus memory space This corresponds to the PCI memory space.
Page 81 CHAPTER 3 MEMORY MANAGEMENT SYSTEM • Reception <1> Set the DMASEN bit of the DMASENREG register of the DCU to 1 to enable DMA sequencer operation. <2> Set the DMAMSKCIN bit of the DMAMSKREG register of the DCU to 1 to enable CSI-reception DMA transfer.
Page 82: Internal I/O Space
CHAPTER 3 MEMORY MANAGEMENT SYSTEM 3.1.4 Internal I/O space Table 3-6 shows the interval I/O space of V 4131. Table 3-6. Internal I/O Space 1 Physical Address Internal I/O 0x0F00 13FF to 0x0F00 1020 0x0F00 101F to 0x0F00 1000 0x0F00 0FFF to 0x0F00 0E00 0x0F00 0DFF to 0x0F00 0C00 0x0F00 0BFF to 0x0F00 0880 0x0F00 087F to 0x0F00 0860...
Page 83: External I/O Address Space
CHAPTER 3 MEMORY MANAGEMENT SYSTEM 3.1.5 External I/O address space The V 4131 has two external I/O spaces. The following table shows each address space. Table 3-7. External I/O Space Physical Address External I/O 0x0DFF FFFF to 0x0C00 0000 External I/O space 1 (IOCS1#) 0x0BFF FFFF to 0x0A00 0000 External I/O space 2 (IOCS0#) 3.1.6 DRAM address space...
Page 84 CHAPTER 3 MEMORY MANAGEMENT SYSTEM (2) Mapping of physical address The area for each bank is determined based on the data bus bit width and the bank capacity, as described below. (a) In 16-bit bus mode (DBUS32 = 0) Bank 3 (CS3#/ROMCS3#): 0x0000 0000 + (Bank 3 capacity + Bank 2 capacity + Bank 1 capacity + Bank 0 capacity) to 0x0000 0000 + (Bank 3 capacity + Bank 1 capacity + Bank 0 capacity + 1 byte) Bank 2 (CS2#/ROMCS2#): 0x0000 0000 + (Bank 2 capacity + Bank 1 capacity + Bank 0 capacity) to 0x0000...
Page 85 CHAPTER 3 MEMORY MANAGEMENT SYSTEM Table 3-9. DRAM Address Example When Using 16 Mb Expansion DRAM (When Using 32-Bit Data Bus) Physical Address When Each Bank Is Set as: Bank 3 = 8 MB, Bank When Each Bank Is Set to 64 MB 2 = 16 MB, Bank 1 = 32 MB, Bank 0 = 64 MB, (SIZE1 = SIZE0 = 5) (SIZE3 = 2, SIZE2 = 3, SIZE1 = 4, SIZE0 = 5)
Page 86: Chapter 4 Exception Processing
CHAPTER 4 EXCEPTION PROCESSING This chapter describes the types of exceptions and the exception processing flow. For the hardware used for exception processing, refer to CHAPTER 5 CP0 REGISTERS. For the details of each exception, refer to the separate V 4100 Series Architecture User's Manual.
Page 87: Priority Of Exceptions
CHAPTER 4 EXCEPTION PROCESSING Table 4-2. 32-Bit Mode Exception Vector Base Addresses Vector Base Address (Virtual) Vector Offset Cold reset 0xBFC0 0000 0x0000 Soft reset (BEV bit is automatically set to 1) TLB refill (EXL = 0) 0x8000 0000 (BEV = 0) 0x0000 0xBFC0 0200 (BEV = 1) XTLB refill (EXL = 0)
Page 88: Exception Processing And Servicing Flowcharts
CHAPTER 4 EXCEPTION PROCESSING 4.2 Exception Processing and Servicing Flowcharts The remainder of this chapter contains flowcharts for the following exception processing and guidelines for their handlers: • Common exceptions and guidelines for their exception handlers • TLB/XTLB refill exceptions and guidelines for exception handlers •...
Page 89 CHAPTER 4 EXCEPTION PROCESSING Figure 4-1. Common Exception Processing (1/2) Start • EntryHi and contextXcontext EntryHi ← VPN2, ASID registers are set only when a Context/Xcontext ← VPN2 TLB refill, TLB invalid, or TLB Setting ExcCode and CE area modified exception occurs. •...
Page 90 CHAPTER 4 EXCEPTION PROCESSING Figure 4-1. Common Exception Processing (2/2) • The unmapped space is used to avoid the occurrence of TLB refill, TLB invalid, and TLB Execute MFC0 instruction modified exceptions. Context/Xcontext register • The EXL bit is set to 1 to avoid the occurrence EPC register of the watch and interrupt exceptions.
Page 91 CHAPTER 4 EXCEPTION PROCESSING Figure 4-2. TLB/XTLB Refill Exception Processing (1/2) Start EntryHi ← VPN2, ASID Context/ XContext ← VPN2 Setting ExcCode and CE area • Check for multiple exceptions EXL bit = 0? M16 bit = 0? Instruction in branch delay slot? Instruction in branch delay slot?
Page 92 CHAPTER 4 EXCEPTION PROCESSING Figure 4-2. TLB/XTLB Refill Exception Processing (2/2) • The unmapped space is used to avoid the occurrence of TLB refill, TLB invalid, and TLB modified exceptions. • The EXL bit is set to 1 to avoid the Execute MFC0 instruction occurrence of the watch and interrupt exceptions.
Page 93 CHAPTER 4 EXCEPTION PROCESSING Figure 4-3. Cold Reset Exception Handling Start ERL bit = 0? M16 bit = 0? Instruction in branch delay slot? Instruction in branch delay slot? BD bit ← 1 BD bit ← 0 ErrorEPC ← PC - 4 ErrorEPC bit ←...
Page 94 CHAPTER 4 EXCEPTION PROCESSING Figure 4-4. Soft Reset and NMI Exception Handling Start ERL bit = 0? M16 bit = 0? Instruction in branch delay slot? Instruction in branch delay slot? BD bit ← 1 BD bit ← 0 ErrorEPC ← PC − 4 ErrorEPC bit ←...
Page 95: Chapter 5 Cp0 Registers
CHAPTER 5 CP0 REGISTERS The CP0 registers support memory management, address translation, exception processing, and privileged operations. This chapter describes the CP0 registers in detail. 5.1 Details of CP0 Registers Table 5-1 lists the CP0 registers. Table 5-1. CP0 Registers Register No.
Page 96: Index Register (0)
CHAPTER 5 CP0 REGISTERS The registers are described in detail below. The number in parentheses indicates the register number. 5.1.1 Index register (0) The index register is a 32-bit, read/write register containing 5 bits to index an entry in the TLB. The most- significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction.
Page 97: Entrylo0 (2) And Entrylo1 (3) Registers
CHAPTER 5 CP0 REGISTERS 5.1.3 EntryLo0 (2) and EntryLo1 (3) registers The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They are used to access the lower bits of the on-chip TLB.
Page 98: Context Register (4)
CHAPTER 5 CP0 REGISTERS Table 5-2. Cache Algorithm C Bit Value Cache Algorithm Cached Cached Uncached Cached Cached Cached Cached Cached 5.1.4 Context register (4) The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array on the memory;...
Page 99: Pagemask Register (5)
CHAPTER 5 CP0 REGISTERS 5.1.5 PageMask register (5) The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison mask that sets the page size for each TLB entry, as shown in Table 5-3. Page sizes must be from 1 KB to 256 KB. TLB read and write instructions use this register as either a source or a destination;...
Page 100: Wired Register (6)
CHAPTER 5 CP0 REGISTERS 5.1.6 Wired register (6) The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 5-6. Wired entries cannot be overwritten by a TLBWR instruction. They can, however, be overwritten by a TLBWI instruction.
Page 101: Bad Virtual Address (Badvaddr) Register (8)
CHAPTER 5 CP0 REGISTERS 5.1.7 Bad Virtual Address (BadVAddr) register (8) The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. Figure 5-8 shows the format of the BadVAddr register.
Page 102: Entryhi Register (10)
CHAPTER 5 CP0 REGISTERS 5.1.9 EntryHi register (10) The EntryHi register is write-accessible. It is used to access the higher bits in the on-chip TLB. The EntryHi register holds the higher bits of a TLB entry for TLB read and write operations. If a TLB refill, TLB invalid, or TLB modified exception occurs, the EntryHi register holds the higher bits of the TLB entry.
Page 103: Compare Register (11)
CHAPTER 5 CP0 REGISTERS 5.1.10 Compare register (11) The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own. When the value of the Count register (refer to 5.1.8 Count register (9)) equals the value of the Compare register, the IP7 bit in the cause register is set.
Page 104 CHAPTER 5 CP0 REGISTERS Figure 5-12. Status Register Format (2/2) Enables 64-bit addressing in kernel mode (0 → 32-bit, 1 → 64-bit). If this bit is set, an XTLB refill exception occurs if a TLB miss occurs in the kernel mode address space. In addition, 64-bit operations are always valid in kernel mode.
Page 105 CHAPTER 5 CP0 REGISTERS (1) Interrupt enable Interrupts are enabled when all of the following conditions are true: • IE is set to 1. • EXL is cleared to 0. • ERL is cleared to 0. • The appropriate bit of the IM is set to 1. (2) Operating modes The following Status register bit settings are required for user, kernel, and supervisor modes.
Page 106: Cause Register (13)
CHAPTER 5 CP0 REGISTERS 5.1.12 Cause register (13) The Cause register is a 32-bit read/write register that holds the cause of the most recent exception. A 5-bit ExcCode (exception code area) indicates one of the causes (refer to Table 5-4). Other bits hold the detailed information of the specific exception.
Page 107 CHAPTER 5 CP0 REGISTERS Table 5-4. Cause Register Exception Code Field Exception Code Mnemonic Description Interrupt exception TLB modified exception TLBL TLB refill exception (load or fetch) TLBS TLB refill exception (store) AdEL Address error exception (load or fetch) AdES Address error exception (store) Bus error exception (instruction fetch) Bus error exception (data load or store)
Page 108: Exception Program Counter (Epc) Register (14)
CHAPTER 5 CP0 REGISTERS 5.1.13 Exception Program Counter (EPC) register (14) The Exception Program Counter (EPC) register is a read/write register that contains the address at which processing resumes after an exception has been processed. The contents of this register change depending on whether execution of MIPS16 instructions is enabled or disabled.
Page 109 CHAPTER 5 CP0 REGISTERS Figure 5-15. EPC Register Format (When MIPS16ISA Is Disabled) (a) 32-bit mode (b) 64-bit mode EPC: Address for a program to be restarted after exception processing. Figure 5-16. EPC Register Format (When MIPS16ISA Is Enabled) (a) 32-bit mode EPC: Exceptional virtual address (31:1).
Page 110: Processor Revision Identifier (Prid) Register (15)
CHAPTER 5 CP0 REGISTERS 5.1.14 Processor Revision Identifier (PRId) register (15) The 32-bit, read-only Processor Revision Identifier (PRId) register contains information identifying the implementation and revision level of the CPU and CP0. Figure 5-17 shows the format of the PRId register. Figure 5-17.
Page 111 CHAPTER 5 CP0 REGISTERS Figure 5-18. Config Register Format (2/2) System interface clock (VTClock) frequency ratio (read only) 0 → RFU 1 → Processor clock frequency divided by 2 2 → RFU 3 → Processor clock frequency divided by 3 4 →...
Page 112: Load Linked Address (Lladdr) Register (17)
CHAPTER 5 CP0 REGISTERS 5.1.16 Load Linked Address (LLAddr) register (17) The Load Linked Address (LLAddr) register is available for read/write and it is used only for diagnostic purposes. This register is defined in the V 4131, to be compatible with the V 4000 and V 4400...
Page 113: Xcontext Register (20)
CHAPTER 5 CP0 REGISTERS 5.1.18 XContext register (20) The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system loads the untranslated data from the PTE into the TLB to handle the error with software.
Page 114: Parity Error Register (26)
CHAPTER 5 CP0 REGISTERS 5.1.19 Parity Error register (26) The Parity Error (PErr) register is a readable/writable register. This register is defined to maintain software- compatibility with the V 4100, and is not used in hardware because the V 4131 has no parity. Figure 5-23 shows the format of the PErr register.
Page 115: Cache Tag Registers (Taglo (28) And Taghi (29))
CHAPTER 5 CP0 REGISTERS 5.1.21 Cache Tag registers (TagLo (28) and TagHi (29)) The TagLo and TagHi registers are 32-bit read/write registers that hold the cache tag during cache initialization, cache diagnostics, or cache error processing. The tag registers are written by the CACHE and MTC0 instructions. Figures 5-25 and 5-26 show the format of these registers.
Page 116: Error Exception Program Counter Errorepc Register (30)
CHAPTER 5 CP0 REGISTERS 5.1.22 Error Exception Program Counter ErrorEPC register (30) The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the program counter value at which the cold reset, soft reset, or NMI exception has been serviced. The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error.
Page 117 CHAPTER 5 CP0 REGISTERS Figure 5-27 shows the format of the ErrorEPC register when the MIPS16ISA is disabled. Figure 5-28 shows the format of the ErrorEPC register when the MIPS16ISA is enabled. Figure 5-27. ErrorEPC Register Format (When MIPS16ISA Is Disabled) (a) 32-bit mode ErrorEPC (b) 64-bit mode...
Page 118: Chapter 6 Initialization Interface
CHAPTER 6 INITIALIZATION INTERFACE This chapter describes the initialization interface and processor modes. It also explains the reset signal descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode that can be selected by the user. Remark # that follows signal names indicates active low.
Page 119 CHAPTER 6 INITIALIZATION INTERFACE During an RTC reset, supplying voltage to the 1.5 V power-supply system (V 1, V P, V PD) can be stopped to reduce the leakage current. The following operation will not be affected by supplying voltage of 1.5 V to these power supplies within the period from when the MPOWER pin becomes active to when PLL starts oscillation.
Page 120 CHAPTER 6 INITIALIZATION INTERFACE When configuring a system that includes the V 4131, it is recommended that at least one or two 3.3 V power supplies be prepared besides the power supply to the V 4131. MPOWER and SPOWER are used in the V 4131 as the power supply control signals for external devices.
Page 121 CHAPTER 6 INITIALIZATION INTERFACE Figure 6-2. Power Supply Control Timing When Using SDRAM Power supply for V 4131 3.3 V Power supply A 3.3 V Power supply B (internal, 32 kHz) Undefined MPOWER (output) SPOWER (output) Shifts to Hiberhate mode RTCRST# (input) Preliminary User’s Manual U15350EJ2V0UM...
Page 122: Rstsw
CHAPTER 6 INITIALIZATION INTERFACE 6.1.2 RSTSW After the RSTSW# pin becomes active and then becomes inactive 100 µ s later, the V 4131 starts PLL oscillation and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation).
Page 123: Software Shutdown
CHAPTER 6 INITIALIZATION INTERFACE 6.1.3 Software shutdown When the software executes the HIBERNATE instruction, the V 4131 sets the DRAM to self refresh mode and sets the MPOWER pin as inactive, then enters reset status. Recovery from reset status occurs when the POWER Note 1 pin is asserted, when a WakeUp timer interrupt occurs, when the DCD# pin is asserted, or when the GPIO(0:3) Note 2...
Page 124 CHAPTER 6 INITIALIZATION INTERFACE After a reset, the processor becomes the system bus master and it begins the cold reset exception sequence to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the 4131, the processor should be completely initialized by software.
Page 125: Haltimer Shutdown
CHAPTER 6 INITIALIZATION INTERFACE 6.1.4 HALTimer shutdown After an RTC reset is canceled, if the HALTimer is not canceled by software within about 4 seconds (the HALTIMERRST bit of the PMUCNTREG register is not set to 1), the V 4131 enters reset status (refer to 12.1.2 Shutdown control).
Page 126: Power-On Sequence
CHAPTER 6 INITIALIZATION INTERFACE 6.2 Power-On Sequence The factors that cause the V 4131 to switch from Hibernate mode or shutdown mode to Fullspeed mode are called power-on factors. There are four power-on factors: assertion of the POWER pin, assertion of the DCD# pin, alarm from the WakeUp timer, and assertion of the GPIO pins (GPIO(0:3), GPIO(9:12)).
Page 127: Reset Of Cpu Core
CHAPTER 6 INITIALIZATION INTERFACE Figure 6-7. V 4131 Activation Sequence (When Not Activating) POWERON (output) MPOW ER (output) 1, V P, V PD 0 V ColdReset# (internal) Reset# (internal) BATTINH/BATTINT# (input) PLL (internal) RTC (internal, 32 kHz) Check BATTINH Detection of CPU not activated /BATTINT# activation factor...
Page 128 CHAPTER 6 INITIALIZATION INTERFACE Once power to the processor is established, the ColdReset# (internal) and the Reset# (internal) signals are asserted and a cold reset is started. After approximately 16 ms from assertion, the ColdReset# signal is deasserted synchronously with MasterOut (internal). Then the Reset# signal is deasserted synchronously with MasterOut, and the cold reset is completed.
Page 129: Soft Reset
CHAPTER 6 INITIALIZATION INTERFACE 6.3.2 Soft reset Caution In the V 4131, a soft reset never occurs. A soft reset initializes the CPU core without affecting the clocks; in other words, a soft reset is a logic reset. In a soft reset, the CPU core retains as much state information as possible;...
Page 130: R 4131 Processor Modes
CHAPTER 6 INITIALIZATION INTERFACE 6.4 V 4131 Processor Modes The V 4131 supports various modes, which can be selected by the user. The CPU core mode is set each time a write occurs in the status register and config register. The on-chip peripheral unit mode is set by writing to the I/O register.
Page 131: Privilege Mode
CHAPTER 6 INITIALIZATION INTERFACE (4) Hibernate mode When a HIBERNATE instruction has been executed, the processor can be set to Hibernate mode. During Hibernate mode, the processor stops supplying clocks to all units. The register and cache contents are retained and output of TClock and MasterOut is stopped.
Page 132: Bootstrap Exception Vector (Bev)
CHAPTER 6 INITIALIZATION INTERFACE 6.4.4 Bootstrap exception vector (BEV) The BEV bit is used to generate an exception during operation testing (diagnostic testing) of the cache and main memory system. When the Status register’s BEV bit has been set, the address of the TLB refill exception vector is changed to the virtual address 0xFFFF FFFF BFC0 0200, the XTLB refill exception vector is changed to the virtual address 0xFFFF FFFF BFC0 0280, and the general exception vector is changed to the address 0xFFFF FFFF BFC0 0380.
Page 133: Chapter 7 Bcu (Bus Control Unit)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.1 Overview The BCU exchanges data with the V 4130 CPU core via the internal SysAD bus inside the V 4131. It also controls an LCD controller, ROM (flash memory or mask ROM), and PCMCIA controller connected to the system bus, and transfers or receives data to or from the above devices via the ADD bus and DATA bus.
Page 134: Bcucntreg1 (0X0F00 0000)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.1 BCUCNTREG1 (0x0F00 0000) (1/2) Name PAGE PAGE PAGE PAGE SIZE[1] SIZE[0] ROM2 ROM0 RTCRST After reset Name ROMW ROMW HLDEN RTCRST After reset Name Function 15:14 Reserved. Write 0 to these bits. 0 is returned when they are read. 13:12 PAGESIZE(1:0) Maximum burst access size for the PageROM to be used.
Page 135 CHAPTER 7 BCU (BUS CONTROL UNIT) (2/2) Name Function Enables PageROM access to the ROM space of bank 1 or 0 (in 16-bit mode) or PAGEROM0 bank 0 (in 32-bit mode). 1: PageROM bus access 0: Normal ROM bus access Reserved.
Page 136: Romsizereg (0X0F00 0004)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.2 ROMSIZEREG (0x0F00 0004) (1/2) Name SIZE32 SIZE31 SIZE30 SIZE22 SIZE21 SIZE20 RTCRST After reset Name SIZE12 SIZE11 SIZE10 SIZE02 SIZE01 SIZE00 RTCRST After reset Name Function Reserved. Write 0 to this bit. 0 is returned when it is read. 14:12 SIZE3(2:0) Selects the ROM capacity of bank 3 (in 16-bit mode) or bank 1 (in 32-bit mode)
Page 137 CHAPTER 7 BCU (BUS CONTROL UNIT) (2/2) Name Function Reserved. Write 0 to this bit. 0 is returned when it is read. SIZE1(2:0) Selects the ROM capacity of bank 1 (in 16-bit mode) or bank 3 (in 32-bit mode). SIZE1(2:0) In 16-bit mode In 32-bit mode (MB)
Page 138: Romspeedreg (0X0F00 0006)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.3 ROMSPEEDREG (0x0F00 0006) Name rom4 rom4 _wait[1] _wait[0] RTCRST After reset Name rom2 rom2 rom2 rom2 _wait[3] _wait[2] _wait[1] _wait[0] RTCRST After reset Name Function 15:14 Reserved. Write 0 to these bits. 0 is returned when they are read. 13:12 rom4_wait[1:0] Selects a page access time of the ROM.
Page 139: Io0Speedreg (0X0F00 0008)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.4 IO0SPEEDREG (0x0F00 0008) Name io0_5 io0_5 io0_3 io0_3 io0_3 io0_3 _wait[1] _wait[0] _wait[3] _wait[2] _wait[1] _wait[0] RTCRST After reset Name io0_2 io0_2 io0_2 io0_2 io0_1 io0_1 io0_1 io0_1 _wait[3] _wait[2] _wait[1] _wait[0] _wait[3] _wait[2] _wait[1] _wait[0]...
Page 140: Io1Speedreg (0X0F00 000A)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.5 IO1SPEEDREG (0x0F00 000A) Name io1_5 io1_5 io1_3 io1_3 io1_3 io1_3 _wait[1] _wait[0] _wait[3] _wait[2] _wait[1] _wait[0] RTCRST After reset Name io1_2 io1_2 io1_2 io1_2 io1_1 io1_1 io1_1 io1_1 _wait[3] _wait[2] _wait[1] _wait[0] _wait[3] _wait[2] _wait[1] _wait[0]...
Page 141: Revidreg (0X0F00 0010)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.6 REVIDREG (0x0F00 0010) Name RID3 RID2 RID1 RID0 MJREV3 MJREV2 MJREV1 MJREV0 RTCRST After reset Note Note Note Note Name MNREV3 MNREV2 MNREV1 MNREV0 RTCRST After reset Note Note Note Note Name Function 15:12 RID(3:0) Processor revision ID.
Page 142: Clkspeedreg (0X0F00 0014)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.7 CLKSPEEDREG (0x0F00 0014) Name TDIVMODE VTDIV VTDIV VTDIV MODE2 MODE1 MODE0 RTCRST Undefined Undefined Undefined Undefined After reset Undefined Undefined Undefined Undefined Name CLKSP4 CLKSP3 CLKSP2 CLKSP1 CLKSP0 RTCRST Undefined Undefined Undefined Undefined Undefined After reset Undefined...
Page 143: Bcucntreg3 (0X0F00 0016)
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.2.8 BCUCNTREG3 (0x0F00 0016) Name EXT_ EXT_ ROMCS1 ROMCS0 RTCRST After reset Hold Hold Name IO32 SYSDIR_ LCDSEL1 LCDSEL0 RTCRST After reset Hold Hold Hold Hold Name Function 15:14 Reserved. Write 0 to these bits. 0 is returned when they are read. 13:12 EXT_ROMCS(1:0) Allocates bank 3 or 2 in 32-bit data bus mode.
Page 144: Connecting Address Pins
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.3 Connecting Address Pins The V 4131 supplies the physical address that the CPU core outputs to ROM/SDRAM/external I/O via the ADD bus. The following table shows the correspondence between the physical address bit output to the ADD bus and the address bit of the external device.
Page 145: Rom Connection
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.3.1 ROM connection Table 7-3 shows an example of connecting the V 4131 to ROM. Table 7-3. Example of ROM Connection and Address Output by V 4131 (1/2) (a) 16-bit data bus mode (DBUS32 = 0) ROM Address Pin With 32 Mb ROM With 64 Mb ROM...
Page 146 CHAPTER 7 BCU (BUS CONTROL UNIT) Table 7-3. Example of ROM Connection and Address Output by V 4131 (2/2) (b) 32-bit data bus mode (DBUS32 = 1) With 32 Mb ROM With 64 Mb ROM With 128 Mb ROM With 256 Mb ROM (2 Mb ×...
Page 147: Notes On Using Bcu
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.4 Notes on Using BCU 7.4.1 Bus mode of CPU core The V 4131 is designed on the assumption that the CPU core is set in the following mode: • Write-back data rate: D •...
Page 148: Rom Interface
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.4.3 ROM interface This section explains the setting and usage of the ROM when it is used with the V 4131. (1) Selecting ROM, PageROM, or flash memory The V 4131 supports three ROM modes for the ROM interface: normal ROM, PageROM, and flash memory. The mode of a ROM bank is selected by using the ROMWEN and PAGEROM bits of BCUCNTREG1.
Page 149 CHAPTER 7 BCU (BUS CONTROL UNIT) (2) Example of write sequence to flash memory Here is an example of a write sequence to the flash memory. Caution The operations in this example are not checked on the actual system. 1. Using a GPIO as an output port, apply a write voltage (V ) to the flash memory.
Page 150: External I/O Interface
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.4.5 External I/O Interface (1) Access size Access an external I/O in 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, or 32 bytes. (2) Data bus size If setting the IO bit of BCUCNTREG3 to 1 in the 32-bit data bus mode (DBUS32 = 1), the V 4131 expands the data bus of an external I/O interface to 32 bits (the default is 16 bits).
Page 151: Load Mitigation Buffer When Sdram Is Used
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.4.6 Load mitigation buffer when SDRAM is used When SDRAM is connected to the V 4131, the load capacitance must be reduced because the address/data bus operates at high speed when the SDRAM is accessed. To reduce the load capacitance, the V 4131 recommends the connection of the address/data bus via the load mitigation buffer when accessing an external I/O space.
Page 152: Bus Operation
CHAPTER 7 BCU (BUS CONTROL UNIT) Figure 7-3. Control Timing of SYSDIR Signal (4-Byte Read Access to I/O Space via 16-Bit Bus) (io0_1_wait = 0000, io0_3_wait = 0000, io0_5_wait = 00, No Wait) VTClock(internal) ADD(24:1) (output) DQM1iADD0j (output) DQM0iSHB#j (output) IOCS0# (output) IORDY...
Page 153 CHAPTER 7 BCU (BUS CONTROL UNIT) (1) Normal ROM read mode To use this mode, it is necessary that ROMWEN = 0 and PAGEROM = 0. The access time of the normal ROM read cycle (Trom) can be selected as shown in Table 7-6, by setting the rom2_wait(2:0) bit of the ROMSPEEDREG register.
Page 154 CHAPTER 7 BCU (BUS CONTROL UNIT) Figure 7-5. ROM 4-Byte Read (32-Bit Mode, rom2_wait(2:0) = 000) Trom VTClock (internal) ADD(24:1) ROMCS(3:0)# DATA(31:0) Remark The dotted line indicates a high-impedance state. The DATA bus is sampled at the rising edge of the VTClock that follows the Trom cycle. The following seven bus operations of the normal ROM can be executed: 1-byte read, 2-byte read, 3-byte read, 1-word read, 2-word read, 4-word read, 8-word read (1 word = 4 bytes)
Page 155 CHAPTER 7 BCU (BUS CONTROL UNIT) Figure 7-6. PageROM 4-Word Read (16-Bit Mode, rom2_wait(2:0) = 001, rom4_wait(1:0) = 00) Trom T prom T prom T prom T prom T prom T prom T prom VTClock (internal) ADD(24:1) ROMCS(3:0)# DATA(15:0) Remark The dotted line indicates a high-impedance state. Figure 7-7.
Page 156: I/O Space Access
CHAPTER 7 BCU (BUS CONTROL UNIT) Figure 7-8. 2-Byte Access of Flash Memory Mode Flash memory mode access cycle VTClock (internal) ADD(24:1) ROMCS(3:0)# RD#/WR# 7.5.2 I/O space access The following table shows the relationship between DQM[0], DQM[1] and the data bus during 16-bit accessing of the V 4131 I/O space.
Page 157 CHAPTER 7 BCU (BUS CONTROL UNIT) Figure 7-9. 4-Byte Access to I/O Space via 16-Bit Bus (io0_1_wait = 0000, io0_3_wait = 0000, io0_5_wait = 00, No Wait) VTClock (internal) ADD(24:1) DQM[1] (ADD[0]) DQM[0] (SHB#) IOCS#(0) IORDY RD#/WR# DATA[15:0] (write) DATA[15:0] (read) Figure 7-10.
Page 158 CHAPTER 7 BCU (BUS CONTROL UNIT) Figure 7-11. Setting Access Time by S/W for 4-Byte Access to I/O Space via 32-Bit Bus (io0_1_wait = 0010, io0_2_wait = 0010, io0_3_wait = 0010, io0_5_wait = 10, No Wait) VTClock (internal) ADD(24:2) DQM[3:0] (BE#[3:0]) IOCS#(0) IORDY...
Page 159: Bus Hold
CHAPTER 7 BCU (BUS CONTROL UNIT) 7.5.3 Bus hold The bus hold function, which enables an external master in the I/O space to access SDRAM directly, is specified below. (1) Control method (a) HLDRQ# and HLDAK# pins • HLDRQ#: Used for bus hold request •...
Page 160: Chapter 8 Dmaau (Dma Address Unit)
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.1 General The DMAAU controls the DMA addresses for the CSI, IrDA 4 Mbps communication module (hereafter called FIR), I/O space and RAM. The DMA start address of each DMA channel can be specified to any physical addresses 0x0000 0000 to 0x01FF FFFE.
Page 161: Dma Between I/O Space And Ram
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.1.2 DMA between I/O space and RAM <1> Write the number of transfer bytes in the BASSCNTLREG and BASSCNTHREG registers and set the values of the CURRENTCNTLREG and CURRENTCNTHREG registers to 0. <2> Write the start address to the DMA address register and execute DMA transfer. At this time, the DMA address register is incremented from the transfer start address by the number of bytes that have been transferred.
Page 162: Register Set
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2 Register Set The DMAAU registers are listed below. Table 8-1. DMAAU Registers Address Register Symbols Function 0x0F00 0020 CSIIBALREG DMA base address lower register for receiving CSI 0x0F00 0022 CSIIBAHREG DMA base address higher register for receiving CSI 0x0F00 0024 CSIIALREG DMA address lower register for the receiving CSI...
Page 163: Dma Base Address Register For Receiving Csi
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.1 DMA base address register for receiving CSI (1) CSIIBALREG (0x0F00 0020) Name CSIIBA15 CSIIBA14 CSIIBA13 CSIIBA12 CSIIBA11 CSIIBA10 CSIIBA9 CSIIBA8 RTCRST After reset Name CSIIBA7 CSIIBA6 CSIIBA5 CSIIBA4 CSIIBA3 CSIIBA2 CSIIBA1 CSIIBA0 RTCRST After reset Name Function...
Page 164: Dma Address Register For Receiving Csi
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.2 DMA address register for receiving CSI (1) CSIIALREG (0x0F00 0024) Name CSIIA15 CSIIA14 CSIIA13 CSIIA12 CSIIA11 CSIIA10 CSIIA9 CSIIA8 RTCRST After reset Name CSIIA7 CSIIA6 CSIIA5 CSIIA4 CSIIA3 CSIIA2 CSIIA1 CSIIA0 RTCRST After reset Name Function 15:2...
Page 165: Dma Base Address Register For Transmitting Csi
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.3 DMA base address register for transmitting CSI (1) CSIOBALREG (0x0F00 0028) Name CSIOBA15 CSIOBA14 CSIOBA13 CSIOBA12 CSIOBA11 CSIOBA10 CSIOBA9 CSIOBA8 RTCRST After reset Name CSIOBA7 CSIOBA6 CSIOBA5 CSIOBA4 CSIOBA3 CSIOBA2 CSIOBA1 CSIOBA0 RTCRST After reset Name Function...
Page 166: Dma Address Register For Transmitting Csi
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.4 DMA address register for transmitting CSI (1) CSIOALREG (0x0F00 002C) Name CSIOA15 CSIOA14 CSIOA13 CSIOA12 CSIOA11 CSIOA10 CSIOA9 CSIOA8 RTCRST After reset Name CSIOA7 CSIOA6 CSIOA5 CSIOA4 CSIOA3 CSIOA2 CSIOA1 CSIOA0 RTCRST After reset Name Function 15:2...
Page 167: Dma Base Address Register For Fir
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.5 DMA base address register for FIR (1) FIRBALREG (0x0F00 0030) Name FIRBA15 FIRBA14 FIRBA13 FIRBA12 FIRBA11 FIRBA10 FIRBA9 FIRBA8 RTCRST After reset Name FIRBA7 FIRBA6 FIRBA5 FIRBA4 FIRBA3 FIRBA2 FIRBA1 FIRBA0 RTCRST After reset Name Function 15:0...
Page 168: Fir Dma Address Registers
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.6 FIR DMA address registers (1) FIRALREG (0x0F00 0034) Name FIRA15 FIRA14 FIRA13 FIRA12 FIRA11 FIRA10 FIRA9 FIRA8 RTCRST After reset Name FIRA7 FIRA6 FIRA5 FIRA4 FIRA3 FIRA2 FIRA1 FIRA0 RTCRST After reset Name Function 15:0 FIRA(15:0)
Page 169: Dma Base Address Register For Ram Space
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.7 DMA base address register for RAM space (1) RAMBALREG (0x0F00 01E0) Name RAMBA15 RAMBA14 RAMBA13 RAMBA12 RAMBA11 RAMBA10 RAMBA9 RAMBA8 RTCRST After reset Name RAMBA7 RAMBA6 RAMBA5 RAMBA4 RAMBA3 RAMBA2 RTCRST After reset Name Function 15:2...
Page 170: Dma Address Register For Ram Space
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.8 DMA address register for RAM space (1) RAMALREG (0x0F00 01E4) Name RAMA15 RAMA14 RAMA13 RAMA12 RAMA11 RAMA10 RAMA9 RAMA8 RTCRST After reset Name RAMA7 RAMA6 RAMA5 RAMA4 RAMA3 RAMA2 RTCRST After reset Name Function 15:2 RAMA(15:2)
Page 171: Dma Base Address Register For I/O Space
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.9 DMA base address register for I/O space (1) IOBALREG (0x0F00 01E8) Name IOBA15 IOBA14 IOBA13 IOBA12 IOBA11 IOBA10 IOBA9 IOBA8 RTCRST After reset Name IOBA7 IOBA6 IOBA5 IOBA4 IOBA3 IOBA2 RTCRST After reset Name Function 15:2...
Page 172: Dma Address Register For I/O Space
CHAPTER 8 DMAAU (DMA ADDRESS UNIT) 8.2.10 DMA address register for I/O space (1) IOALREG (0x0F00 01EC) Name IOA15 IOA14 IOA13 IOA12 IOA11 IOA10 IOA9 IOA8 RTCRST After reset Name IOA7 IOA6 IOA5 IOA4 IOA3 IOA2 RTCRST After reset Name Function 15:2 IOA(15:2)
Page 173: Chapter 9 Dcu (Dma Control Unit)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.1 General The DCU is used for DMA control. It controls DMA requests from each on-chip peripheral I/O unit and enables/disables the DMA operation. 9.2 DMA Priority Control When a conflict occurs between DMA requests sent from on-chip peripheral I/O units, the DCU handles DMA requests in the following priority order.
Page 174: Dmarstreg (0X0F00 0040)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.1 DMARSTREG (0x0F00 0040) Name RTCRST After reset Name DMARST RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. DMARST Resets DMA controller. 0: Reset 1: Normal This register is used to reset the DMA controller. 9.3.2 DMAIDLEREG (0x0F00 0042) Name RTCRST...
Page 175: Dmasenreg (0X0F00 0044)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.3 DMASENREG (0x0F00 0044) Name RTCRST After reset Name DMASEN RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. DMASEN Enables DMA sequencer. 1: Enable 0: Disable This register enables or disables the operation of the DMA sequencer (CSI transmission, CSI reception, FIR transmission/reception, I/O space ⇔...
Page 176: Dmamskreg (0X0F00 0046)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.4 DMAMSKREG (0x0F00 0046) Name RTCRST After reset Name DMAMSK DMAMSK DMAMSK DMAMSK COUT FOUT RTCRST After reset Name Function 15:4 Reserved. Write 0. 0 is returned after a read. DMAMSKIOR Enables the I/O space and RAM transfer. 1: Enable 0: Disable DMAMSKCOUT...
Page 177: Dmareqreg (0X0F00 0048)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.5 DMAREQREG (0x0F00 0048) Name RTCRST After reset Name DRQIOR DRQCOUT DRQCIN DRQFOUT RTCRST After reset Name Function 15:4 Reserved. Write 0. 0 is returned after a read. DRQIOR Requests the I/O space and RAM transfer. 1: Request 0: Halt DRQCOUT...
Page 178: Tdreg (0X0F00 004A)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.6 TDREG (0x0F00 004A) Name RTCRST After reset Name IORAM RTCRST After reset Name Function 15:2 Reserved. Write 0. 0 is returned after a read. IORAM Transfer direction of the DMA channel between the I/O space and RAM. 1: External I/O →...
Page 179: Dmaabitreg (0X0F00 004C)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.7 DMAABITREG (0x0F00 004C) Name RTCRST After reset Name DMAPRI3 DMAPRI2 DMAPRI1 DMAPRI0 RTCRST After reset Name Function 15:4 Reserved. Write 0. 0 is returned after a read. DMAPRI(3:0) Selects the DMA arbitration protocol. 1000: Priority to I/O space and RAM space transfer 0100: Priority to CSI transmission 0010: Priority to CSI reception...
Page 180: Controlreg (0X0F00 004E)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.8 CONTROLREG (0x0F00 004E) Name RTCRST After reset Name FIREX DMABLKS1 DMABLKS0 AUTOINIT RTCRST After reset Name Function 15:4 Reserved. Write 0. 0 is returned after a read. FIREX FIRDMA space extended bit 1: 2 KB 2 pages 0: 1 KB 2 pages DMABLKS(1:0) Block size during DMA transfer...
Page 181: Basscntlreg (0X0F00 0050)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.9 BASSCNTLREG (0x0F00 0050) Name DMABS15 DMABS14 DMABS13 DMABS12 DMABS11 DMABS10 DMABS9 DMABS8 RTCRST After reset Name DMABS7 DMABS6 DMABS5 DMABS4 DMABS3 DMABS2 RTCRST After reset Name Function 15:2 DMABS(15:2) Sets the number of transfer bytes for the I/O space and RAM transfer. Reserved.
Page 182: Currentcntlreg (0X0F00 0054)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.11 CURRENTCNTLREG (0x0F00 0054) Name RBS15 RBS14 RBS13 RBS12 RBS11 RBS10 RBS9 RBS8 RTCRST After reset Name RBS7 RBS6 RBS5 RBS4 RBS3 RBS2 RTCRST After reset Name Function 15:2 DMARBS(15:2) Sets the number of transfer blocks for the remaining of the I/O space and RAM transfer. Reserved.
Page 183: Tcintreg (0X0F00 0058)
CHAPTER 9 DCU (DMA CONTROL UNIT) 9.3.13 TCINTREG (0x0F00 0058) Name RTCRST After reset Name TCINT RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. TCINT Interrupt request for the terminal count 1: Available 0: Not available This register is used to indicate the interrupt request for the terminal count.
Page 184: Chapter 10 Cmu (Clock Mask Unit)
CHAPTER 10 CMU (CLOCK MASK UNIT) 10.1 General When internal clocks are supplied from the CPU to each unit, the CMU controls whether the clocks are masked or not. This masking method enables power consumption to be reduced in units that are not used. The units for which CMU is used are the SIU, DSIU, FIR, CSI, and PCIU units.
Page 185: Register Set
CHAPTER 10 CMU (CLOCK MASK UNIT) 10.2 Register Set The CMU register is shown below. Table 10-1. CMU Register Address Register Symbol Function 0x0F00 0060 CMUCLKMSK CMU clock mask register This register is described in detail below. Preliminary User’s Manual U15350EJ2V0UM...
Page 186: Cmuclkmsk (0X0F00 0060)
CHAPTER 10 CMU (CLOCK MASK UNIT) 10.2.1 CMUCLKMSK (0x0F00 0060) Name MSKPCIU MSKSCSI MSKDSIU MSKFFIR MSKSSIU RTCRST After reset Name MSKPCIU MSKCSI MSKFIR MSKSIU RTCRST After reset Name Function 15:14 Reserved. Write 0 to these bits. 0 is returned after a read. MSKPCIU Control of PCLK supplied to PCI interface 1: Supply...
Page 187: Chapter 11 Icu (Interrupt Control Unit)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.1 General The ICU collects interrupt requests from the various on-chip peripheral units and generates interrupt request signals (Int0, Int1, Int2, and NMI) to the CPU core. The functions of the ICU’s internal blocks are briefly described below. •...
Page 188 CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) How an interrupt request is reported to the CPU core is shown below. If an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt indication register of level 2 (xxxINTREG) is set to 1. The interrupt indication register is ANDed bitwise with the corresponding interrupt mask register of level 2 (MxxxINTREG).
Page 189 CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) Figure 11-1. Interrupt Control Outline Level 2 Level 1 siuint ledint SOFTINTREG BCUINTREG AND/OR MBCUINTREG FIRINTREG AND/OR SYSINT1REG MFIRINTREG SYSINT2REG DSIUINTREG AND/OR MDSIUINTREG Note (battint GIUINTLREG AND/OR MGIUINTLREG Int2 GIUINTHREG AND/OR (rtclong2int) MGIUINTHREG AND/OR CSIINTREG Int1 AND/OR...
Page 190: Register Set
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2 Register Set The ICU registers are listed below. Table 11-1. ICU Registers Address Register Symbols Function 0x0F00 0080 SYSINT1REG System interrupt register 1 (level 1) 0x0F00 0088 GIUINTLREG GIU interrupt lower register (level 2) 0x0F00 008A DSIUINTREG DSIU interrupt register (level 2)
Page 191: Sysint1Reg (0X0F00 0080)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.1 SYSINT1REG (0x0F00 0080) Name CLKRUN SOFT SIUINTR GIUINTR INTR INTR RTCRST After reset Name ETIMER RTCL1 POWER BATINTR INTR INTR INTR RTCRST After reset Name Function 15:13 Reserved. Write 0. 0 is returned after a read. CLKRUNINTR CLKRUN interrupt request 1: Occurred...
Page 192: Giuintlreg (0X0F00 0088)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.2 GIUINTLREG (0x0F00 0088) Name INTS15 INTS13 INTS12 INTS11 INTS10 INTS9 INTS8 RTCRST After reset Name INTS7 INTS6 INTS5 INTS4 INTS3 INTS2 INTS1 INTS0 RTCRST After reset Name Function INTS15 Inputs interrupt request to GPIO(15) pin. 1: Occurred 0: Normal Reserved.
Page 193: Dsiuintreg (0X0F00 008A)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.3 DSIUINTREG (0x0F00 008A) Name INTDSIU RTCRST After reset Name RTCRST After reset Name Function 15:12 Reserved. Write 0. 0 is returned after a read. INTDSIU Interrupt request from DSIU 1: Occurred 0: Normal 10:0 Reserved.
Page 194: Msysint1Reg (0X0F00 008C)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.4 MSYSINT1REG (0x0F00 008C) Name CLKRUN SOFT SIUINTR GIUINTR INTR INTR RTCRST After reset Name ETIMER RTCL1 POWER BATINTR INTR INTR INTR RTCRST After reset Name Function 15:13 Reserved. Write 0. 0 is returned after a read. CLKRUNINTR CLKRUN interrupt enable 1: Enable...
Page 195: Mgiuintlreg (0X0F00 0094)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.5 MGIUINTLREG (0x0F00 0094) Name INTS15 INTS13 INTS12 INTS11 INTS10 INTS9 INTS8 RTCRST After reset Name INTS7 INTS6 INTS5 INTS4 INTS3 INTS2 INTS1 INTS0 RTCRST After reset Name Function INTS15 Interrupt input enable to GPIO(15) pin 1: Enable 0: Disable Reserved.
Page 196: Mdsiuintreg (0X0F00 0096)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.6 MDSIUINTREG (0x0F00 0096) Name INTDSIU RTCRST After reset Name RTCRST After reset Name Function 15:12 Reserved. Write 0. 0 is returned after a read. INTDSIU DSIU interrupt enable 1: Enable 0: Disable 10:0 Reserved.
Page 197: Nmireg (0X0F00 0098)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.7 NMIREG (0x0F00 0098) Name RTCRST After reset Name NMIOR RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. NMIORINT Reports low battery detect interrupt request. 1: Int0 0: NMI This register is used to set the type of interrupt request used to notify the V 4130 CPU core when a low battery...
Page 198: Softintreg (0X0F00 009A)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.8 SOFTINTREG (0x0F00 009A) Name RTCRST After reset Name SOFT SOFT SOFT SOFT INTR3 INTR2 INTR1 INTR0 RTCRST After reset Name Function 15:4 Reserved. Write 0. 0 is returned after a read. SOFTINTR(3:0) Software interrupt request 1: Set 0: Clear This register is used to generate software interrupts.
Page 199: Sysint2Reg (0X0F00 00A0)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.9 SYSINT2REG (0x0F00 00A0) Name INTR INTR RTCRST After reset Name DSIU TCLK RTCL2 INTR INTR INTR INTR INTR INTR INTR RTCRST After reset Name Function 15:10 Reserved. Write 0. 0 is returned after a read. BCUINTR BCU interrupt request 1: Occurred...
Page 200: Giuinthreg (0X0F00 00A2)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.10 GIUINTHREG (0x0F00 00A2) Name INTS31 INTS30 INTS29 INTS28 INTS27 INTS26 INTS25 INTS24 RTCRST After reset Name INTS23 INTS22 INTS21 INTS20 INTS19 INTS18 INTS17 INTS16 RTCRST After reset Name Function 15:0 INTS(31:16) Inputs interrupt request to GPIO(31:16) pins 1: Occurred 0: Normal This register indicates whether various GIU-related interrupt requests occur.
Page 201: Firintreg (0X0F00 00A4)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.11 FIRINTREG (0x0F00 00A4) Name RTCRST After reset Name FIRINT FDPINT4 FDPINT3 FDPINT2 FDPINT1 RTCRST After reset Name Function 15:5 Reserved. Write 0. 0 is returned after a read. FIRINT Interrupt request from FIR unit 1: Occurred 0: Normal FDPINT4...
Page 202: Msysint2Reg (0X0F00 00A6)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.12 MSYSINT2REG (0x0F00 00A6) Name INTR INTR RTCRST After reset Name DSIU TCLK LEDINTR RTCL2 INTR INTR INTR INTR INTR INTR RTCRST After reset Name Function 15:10 Reserved. Write 0. 0 is returned after a read. BCUINTR BCU interrupt enable 1: Enable...
Page 203: Mgiuinthreg (0X0F00 00A8)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.13 MGIUINTHREG (0x0F00 00A8) Name INTS31 INTS30 INTS29 INTS28 INTS27 INTS26 INTS25 INTS24 RTCRST After reset Name INTS23 INTS22 INTS21 INTS20 INTS19 INTS18 INTS17 INTS16 RTCRST After reset Name Function 15:0 INTS(31:16) Interrupt input enable to GPIO(31:16) pins 1: Enable 0: Disable This register is used to mask various GIU-related interrupt requests.
Page 204: Mfirintreg (0X0F00 00Aa)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.14 MFIRINTREG (0x0F00 00AA) Name RTCRST After reset Name FIRINT FDPINT4 FDPINT3 FDPINT2 FDPINT1 RTCRST After reset Name Function 15:5 Reserved. Write 0 to these bits. 0 is returned after a read. FIRINT FIR unit interrupt enable 1: Enable 0: Disable FDPINT4...
Page 205: Pciintreg (0X0F00 00Ac)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.15 PCIINTREG (0x0F00 00AC) Name RTCRST After reset Name PCIINT0 RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. PCIINT0 Interrupt request from PCI macro 1: Occurred 0: Normal This register indicates whether various PCI-related interrupt requests occur.
Page 206: Scuintreg (0X0F00 00Ae)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.16 SCUINTREG (0x0F00 00AE) Name RTCRST After reset Name SCUINT0 RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. SCUINT0 SCU interrupt request 1: Occurred 0: Normal This register indicates whether various SCU-related interrupt requests occur. Preliminary User’s Manual U15350EJ2V0UM...
Page 207: Csiintreg (0X0F00 00B0)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.17 CSIINTREG (0x0F00 00B0) Name RTCRST After reset Name TRPAGE2 TRPAGE1 TREND TREMPTY RCPAGE2 RCPAGE1 RCOVER RTCRST After reset Name Function 15:7 Reserved. Write 0. 0 is returned after a read. TRPAGE2 DMA transmit 2-page interrupt 1: Occurred 0: Normal TRPAGE1...
Page 208: Mpciintreg (0X0F00 00B2)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.18 MPCIINTREG (0x0F00 00B2) Name RTCRST After reset Name PCIINT0 RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. PCIINT0 PCI interrupt enable 1: Enable 0: Disable This register is used to mask various PCI-related interrupt requests. Preliminary User’s Manual U15350EJ2V0UM...
Page 209: Mscuintreg (0X0F00 00B4)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.19 MSCUINTREG (0x0F00 00B4) Name RTCRST After reset Name SCUINT0 RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. SCUINT0 SCU interrupt enable 1: Enable 0: Disable This register is used to mask various SCU-related interrupt requests. Preliminary User’s Manual U15350EJ2V0UM...
Page 210: Mcsiintreg (0X0F00 00B6)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.20 MCSIINTREG (0x0F00 00B6) Name RTCRST After reset Name TRPAGE2 TRPAGE1 TREND TREMPTY RCPAGE2 RCPAGE1 RCOVER RTCRST After reset Name Function 15:7 Reserved. Write 0. 0 is returned after a read. TRPAGE2 DMA transmit 2-page interrupt enable 1: Enable 0: Disable TRPAGE1...
Page 211: Bcuintreg (0X0F00 00B8)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.21 BCUINTREG (0x0F00 00B8) Name RTCRST After reset Name BCUINTR RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. BCUINTR BCU interrupt request 1: Occurred 0: Normal This register indicates whether various BCU-related interrupt requests occur. Preliminary User’s Manual U15350EJ2V0UM...
Page 212: Mbcuintreg (0X0F00 00Ba)
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.2.22 MBCUINTREG (0x0F00 00BA) Name RTCRST After reset Name MBCUINT RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. MBCUINTR BCU interrupt enable 1: Enable 0: Disable This register is used to set various BCU interrupt request masks. Preliminary User’s Manual U15350EJ2V0UM...
Page 213: Notes For Register Setting
CHAPTER 11 ICU (INTERRUPT CONTROL UNIT) 11.3 Notes for Register Setting There is no register setting flow in relation to the ICU. With regard to each interrupt mask register, the initial setting is 0 (mask) after reset. Therefore, enough masks must be cleared to provide sufficient interrupts for the CPU’s start-up processing.
Page 214: Chapter 12 Pmu (Power Management Unit)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.1 General The PMU performs the following power management within the V 4131 and controls the power supply throughout the system that includes the V 4131. • Reset control • Shutdown control • Power-on control •...
Page 215: Shutdown Control
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.1.2 Shutdown control The operations of the RTC, peripheral units, and CPU core, and the bits set by the PMUINTREG and PMUCNTREG registers are listed below. Table 12-2. Bit Operations During Shutdown Shutdown Type Peripheral Units CPU Core Set Bit...
Page 216: Power-On Control
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.1.3 Power-on control The causes of CPU activation (mode change from shutdown or Hibernate mode to Fullspeed mode) are called startup factors. There are eleven startup factors: a power switch interrupt (POWER), eight types of GPIO activation interrupts (GPIO(3:0), (12:9)), a DCD interrupt (DCD#), and an Elapsed Time timer interrupt.
Page 217 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) (1) Activation via power switch interrupt When the POWER signal becomes active (if the rising edge of POWER is detected by the PMU), the PMU makes the POWERON signal active and provides external notification that the CPU is being activated. After making the POWERON signal active, the PMU checks the BATTINH/BATTINT# signal and then makes the POWERON signal inactive.
Page 218 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) (2) Activation via GPIO activation interrupt When the GPIO(3:0) and GPIO(12:9) signals become active, the PMU checks the activation interrupt enable bit for GPIO(3:0) and GPIO(12:9). If GPIO(3:0) and GPIO(12:9) activation interrupts are enabled, the PMU makes the POWERON signal active and provides external notification that the CPU is being activated (since the GPIO(2:0) and GPIO(12:9) activation enable interrupt bit is cleared after an RTC is reset, the GPIO(2:0) and GPIO(12:9) signals cannot be used for activation immediately after an RTC reset.
Page 219 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) (3) Activation via DCD interrupt When the DCD# signal becomes active (it means, the falling edge of DCD# signal is detected by PMU), the PMU makes the POWERON signal active and provides external notification that the CPU is being started. After making the POWERON signal active, the PMU checks the BATTINH/BATTINT# signal and then makes the POWERON signal inactive.
Page 220 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) (4) Activation via Elapsed Time timer interrupt When the alarm interrupt (alarm_intr) signal generated from the Elapsed Time timer becomes active, the PMU makes the POWERON signal active and provides external notification that the CPU is being activated. After making the POWERON signal active, the PMU checks the BATTINH/BATTINT# signal and then makes the POWERON signal inactive.
Page 221: Power Mode
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.1.4 Power mode The V 4131 supports the following five power modes. • Fullspeed mode • Standby mode • Suspend mode • Exsuspend mode • Hibernate mode To set Standby, Suspend, Exsuspend, or Hibernate mode from Fullspeed mode, execute the STANDBY, SUSPEND, or HIBERNATE instruction, respectively.
Page 222 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) Figure 12-9. Power Mode State Transition Suspend Standby mode and mode Exsuspend mode Fullspeed mode Hibernate mode STANDBY All interrupts SUSPEND POWER HIBERNATE POWER instruction, instruction, RSTSW instruction, Elapsed Time pipeline flash, pipeline flash, Elapsed Time pipeline flash, DCD#...
Page 223 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) (1) Fullspeed mode In Fullspeed mode, all internal clocks and the bus clock operate. In this mode, all the functions of the V 4131 can be executed. (2) Standby mode In Standby mode, all internal clocks, other than those provided for the on-chip peripheral units and the internal timer/interrupt unit of the CPU core, are fixed to high level.
Page 224: Register Set
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) • GPIO pins as startup factors The GPIO(12:9) and GPIO(3:0) pins can be used not only as general-purpose ports and interrupt request inputs but also as startup factors from Hibernate mode. In addition, the GPIO3 pin can be used as a startup factor that follows an RTC reset.
Page 225: Pmuintreg (0X0F00 00C0)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.2.1 PMUINTREG (0x0F00 00C0) (1/2) Name GPIO3 GPIO2 GPIO1 GPIO0 CLKRUN DCDST RTCINTR BATTINH INTR INTR INTR INTR INTR RTCRST After reset Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Name...
Page 226 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) (2/2) Name Function memo(1:0) Memo. These bits are readable/writable, and can be used by users freely. TIMOUTRST HALTimer reset detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected RTCRST RTC reset detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected RSTSW...
Page 227: Pmucntreg (0X0F00 00C2)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.2.2 PMUCNTREG (0x0F00 00C2) (1/2) Name GPIO3MSK GPIO2MSK GPIO1MSK GPIO0MSK GPIO3TRG GPIO2TRG GPIO1TRG GPIO0TRG RTCRST After reset Note Note Note Note Note Note Note Note Name STANDBY PLLOFFEN HALTIMER RTCRST After reset Name Function GPIO3MSK GPIO3 activation enable 1: Enable...
Page 228 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) (2/2) Name Function Reserved. Write 0. 0 is returned after a read. PLLOFFEN PLL halt enable during Suspend mode 1: PLL halt (Exsuspend mode) 0: PLL operation HALTIMERRST HALTimer reset 1: Reset 0: Set Reserved.
Page 229: Pmuint2Reg (0X0F00 00C4)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.2.3 PMUINT2REG (0x0F00 00C4) Name GPIO12 GPIO11 GPIO10 GPIO9 INTR INTR INTR INTR RTCRST After reset Name RTCRST After reset Name Function GPIO12INTR GPIO12 activation interrupt request detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected GPIO11INTR...
Page 230: Pmucnt2Reg (0X0F00 00C6)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.2.4 PMUCNT2REG (0x0F00 00C6) Name GPIO12 GPIO11 GPIO10 GPIO9 GPIO12 GPIO11 GPIO10 GPIO9 RTCRST After reset Note Note Note Note Note Note Note Note Name SOFTRST RTCRST After reset Name Function GPIO12MSK GPIO12 activation enable 1: Enable 0: Disable GPIO11MSK...
Page 231 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) This register performs various settings for activation by the GPIO(12:9) interrupt and sets the software reset switch. The GPIO(12:9)MSK bits are used to set enable/disable for activation from Hibernate mode when the corresponding interrupt (GPIO(12:9)) occurs. All mask bits are cleared to 0 (disable) by RTCRST. Therefore, GPIO(12:9) interrupts cannot be used for activation immediately after the RTCRST reset.
Page 232: Pmuwaitreg (0X0F00 00C8)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.2.5 PMUWAITREG (0x0F00 00C8) Name WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT RTCRST After reset Note Note Note Note Note Note Name WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT RTCRST After reset Note Note Note Note Note...
Page 233: Pmutclkdivreg (0X0F00 00Cc)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.2.6 PMUTCLKDIVREG (0x0F00 00CC) Name TDIV RTCRST After reset Note Name VTDIV2 VTDIV1 VTDIV0 RTCRST After reset Note Note Note Name Function 15:9 Reserved. Write 0. 0 is returned after a read. TDIV TCLK division ratio setting 1: 1/4 VTClock 0: 1/2 VTClock Reserved.
Page 234 CHAPTER 12 PMU (POWER MANAGEMENT UNIT) Table 12-6. CLKSEL(2:0) Pins and Frequency of PClock, VTClock, TClock and MasterOut (Default Value) CLKSEL(2:0) PClock (MHz) VTClock (MHz) TClock (MHz) MasterOut (MHz) 199.1 33.2 16.6 4.15 181.0 30.2 15.1 3.775 165.9 33.2 16.6 4.15 153.1 30.6...
Page 235: Pmuintrclkdivreg (0X0F00 00Ce)
CHAPTER 12 PMU (POWER MANAGEMENT UNIT) 12.2.7 PMUINTRCLKDIVREG (0x0F00 00CE) Name RTCRST After reset Name IDIV1 IDIV0 RTCRST After reset Note Note Name Function 15:2 Reserved. Write 0. 0 is returned after a read. IDIV(1:0) intrclk clock division ratio setting. 11: RFU 10: 1/4 01: 1/8...
Page 236: Chapter 13 Rtc (Realtime Clock Unit)
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.1 General The RTC unit has a total of four timers, including the following three types. • RTC Long timer ..This is a 24-bit programmable counter that counts down using 32.768 kHz frequency. The RTC unit includes two RTC Long timers.
Page 237: Register Set
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2 Register Set The following table shows the RTC registers. Table 13-1. RTC Registers Address Register Symbol Function 0x0F00 0100 ETIMELREG Elapsed Time timer lower register 0x0F00 0102 ETIMEMREG Elapsed Time timer middle register 0x0F00 0104 ETIMEHREG Elapsed Time timer higher register...
Page 238: Elapsed Time Timer Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.1 Elapsed Time timer registers (1) ETIMELREG (0x0F00 0100) Name ETIME15 ETIME14 ETIME13 ETIME12 ETIME11 ETIME10 ETIME9 ETIME8 RTCRST After reset Note Note Note Note Note Note Note Note Name ETIME7 ETIME6 ETIME5 ETIME4 ETIME3 ETIME2 ETIME1...
Page 239 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (3) ETIMEHREG (0x0F00 0104) Name ETIME47 ETIME46 ETIME45 ETIME44 ETIME43 ETIME42 ETIME41 ETIME40 RTCRST After reset Note Note Note Note Note Note Note Note Name ETIME39 ETIME38 ETIME37 ETIME36 ETIME35 ETIME34 ETIME33 ETIME32 RTCRST After reset Note Note...
Page 240: Elapsed Time Timer Compare Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.2 Elapsed Time timer compare registers (1) ECMPLREG (0x0F00 0108) Name ECMP15 ECMP14 ECMP13 ECMP12 ECMP11 ECMP10 ECMP9 ECMP8 RTCRST After reset Note Note Note Note Note Note Note Note Name ECMP7 ECMP6 ECMP5 ECMP4 ECMP3 ECMP2...
Page 241 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (3) ECMPHREG (0x0F00 010C) Name ECMP47 ECMP46 ECMP45 ECMP44 ECMP43 ECMP42 ECMP41 ECMP40 RTCRST After reset Note Note Note Note Note Note Note Note Name ECMP39 ECMP38 ECMP37 ECMP36 ECMP35 ECMP34 ECMP33 ECMP32 RTCRST After reset Note Note...
Page 242: Rtc Long1 Timer Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.3 RTC Long1 timer registers (1) RTCL1LREG (0x0F00 0110) Name RTCL1P15 RTCL1P14 RTCL1P13 RTCL1P12 RTCL1P11 RTCL1P10 RTCL1P9 RTCL1P8 RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL1P7 RTCL1P6 RTCL1P5 RTCL1P4 RTCL1P3 RTCL1P2 RTCL1P1...
Page 243 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (2) RTCL1HREG (0x0F00 0112) Name RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL1P23 RTCL1P22 RTCL1P21 RTCL1P20 RTCL1P19 RTCL1P18 RTCL1P17 RTCL1P16 RTCRST After reset Note Note Note Note Note Note Note Note Name...
Page 244: Rtc Long1 Timer Count Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.4 RTC Long1 timer count registers (1) RTCL1CNTLREG (0x0F00 0114) Name RTCL1C15 RTCL1C14 RTCL1C13 RTCL1C12 RTCL1C11 RTCL1C10 RTCL1C9 RTCL1C8 RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL1C7 RTCL1C6 RTCL1C5 RTCL1C4 RTCL1C3 RTCL1C2...
Page 245 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (2) RTCL1CNTHREG (0x0F00 0116) Name RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL1C23 RTCL1C22 RTCL1C21 RTCL1C20 RTCL1C19 RTCL1C18 RTCL1C17 RTCL1C16 RTCRST After reset Note Note Note Note Note Note Note Note Name...
Page 246: Rtc Long2 Timer Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.5 RTC Long2 timer registers (1) RTCL2LREG (0x0F00 0118) Name RTCL2P15 RTCL2P14 RTCL2P13 RTCL2P12 RTCL2P11 RTCL2P10 RTCL2P9 RTCL2P8 RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL2P7 RTCL2P6 RTCL2P5 RTCL2P4 RTCL2P3 RTCL2P2 RTCL2P1...
Page 247 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (2) RTCL2HREG (0x0F00 011A) Name RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL2P23 RTCL2P22 RTCL2P21 RTCL2P20 RTCL2P19 RTCL2P18 RTCL2P17 RTCL2P16 RTCRST After reset Note Note Note Note Note Note Note Note Name...
Page 248: Rtc Long2 Timer Count Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.6 RTC Long2 timer count registers (1) RTCL2CNTLREG (0x0F00 011C) Name RTCL2C15 RTCL2C14 RTCL2C13 RTCL2C12 RTCL2C11 RTCL2C10 RTCL2C9 RTCL2C8 RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL2C7 RTCL2C6 RTCL2C5 RTCL2C4 RTCL2C3 RTCL2C2...
Page 249 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (2) RTCL2CNTHREG (0x0F00 011E) Name RTCRST After reset Note Note Note Note Note Note Note Note Name RTCL2C23 RTCL2C22 RTCL2C21 RTCL2C20 RTCL2C19 RTCL2C18 RTCL2C17 RTCL2C16 RTCRST After reset Note Note Note Note Note Note Note Note Name...
Page 250: Tclock Counter Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.7 TClock counter registers (1) TCLKLREG (0x0F00 0120) Name TCLKP15 TCLKP14 TCLKP13 TCLKP12 TCLKP11 TCLKP10 TCLKP9 TCLKP8 RTCRST After reset Name TCLKP7 TCLKP6 TCLKP5 TCLKP4 TCLKP3 TCLKP2 TCLKP1 TCLKP0 RTCRST After reset Name Function 15:0 TCLKP(15:0) Bit 15:0 for TClock counter cycle...
Page 251 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (2) TCLKHREG (0x0F00 0122) Name TCLKP24 RTCRST After reset Name TCLKP23 TCLKP22 TCLKP21 TCLKP20 TCLKP19 TCLKP18 TCLKP17 TCLKP16 RTCRST After reset Name Function 15:9 Reserved. Write 0. 0 is returned after a read. TCLKP(24:16) Bit 24:16 for TClock counter cycle Set the TClock counter cycle to these registers.
Page 252: Tclock Counter Count Registers
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.8 TClock counter count registers (1) TCLKCNTLREG (0x0F00 0124) Name TCLKC15 TCLKC14 TCLKC13 TCLKC12 TCLKC11 TCLKC10 TCLKC9 TCLKC8 RTCRST After reset Name TCLKC7 TCLKC6 TCLKC5 TCLKC4 TCLKC3 TCLKC2 TCLKC1 TCLKC0 RTCRST After reset Name Function 15:0 TCLKC(15:0)
Page 253 CHAPTER 13 RTC (REALTIME CLOCK UNIT) (2) TCLKCNTHREG (0x0F00 0126) Name TCLKC24 RTCRST After reset Name TCLKC23 TCLKC22 TCLKC21 TCLKC20 TCLKC19 TCLKC18 TCLKC17 TCLKC16 RTCRST After reset Name Function 15:9 Reserved. Write 0. 0 is returned after a read. TCLKC(24:16) TClock counter bit 24:16 These registers indicate the TClock counter’s values.
Page 254: Rtc Interrupt Register
CHAPTER 13 RTC (REALTIME CLOCK UNIT) 13.2.9 RTC interrupt register (1) RTCINTREG (0x0F00 013E) Name RTCRST After reset Name RTCINTR3 RTCINTR2 RTCINTR1 RTCINTR0 RTCRST After reset Note Note Note Name Function 15:4 Reserved. Write 0. 0 is returned after a read. RTCINTR3 TClock counter interrupt request.
Page 255: Chapter 14 Giu (General-Purpose I/O Unit)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.1 Outline The GIU controls the GPIO and DCD# pins. The GPIO pins are general-purpose ports for which input and output are available. An interrupt request signal input function can be assigned to GPIO with input signal change (rising edge or falling edge of signal), low level, or high level used as the trigger.
Page 256: Register Set
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2 Register Set The GIU registers are listed below. Table 14-2. GIU Registers Address Register Symbol Function 0x0F00 0140 GIUIOSELL GPIO input/output setting lower register 0x0F00 0142 GIUIOSELH GPIO input/output setting higher register 0x0F00 0144 GIUPIODL GPIO input/output data lower register 0x0F00 0146...
Page 257: Giuiosell (0X0F00 0140)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.1 GIUIOSELL (0x0F00 0140) Name IOS15 IOS13 IOS12 IOS11 IOS10 IOS9 IOS8 RTCRST After reset Name IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 RTCRST After reset Name Function IOS15 Selects GPIO15(DCD#) pin input/output. 1: RFU 0: Input Reserved.
Page 258: Giuioselh (0X0F00 0142)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.2 GIUIOSELH (0x0F00 0142) Name IOS31 IOS30 IOS29 IOS28 IOS27 IOS26 IOS25 IOS24 RTCRST After reset Name IOS23 IOS22 IOS21 IOS20 IOS19 IOS18 IOS17 IOS16 RTCRST After reset Name Function 15:0 IOS(31:16) Selects GPIO(31:16) pin input/output. 1: Output 0: Input This register sets the I/O mode of the GPIO(31:16) pins.
Page 259: Giupiodl (0X0F00 0144)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.3 GIUPIODL (0x0F00 0144) Name PIOD15 PIOD13 PIOD12 PIOD11 PIOD10 PIOD9 PIOD8 RTCRST After reset Name PIOD7 PIOD6 PIOD5 PIOD4 PIOD3 PIOD2 PIOD1 PIOD0 RTCRST After reset Name Function PIOD15 Specifies GPIO15(DCD#) pin output data. 1: RFU 0: Low level Reserved.
Page 260: Giupiodh (0X0F00 0146)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.4 GIUPIODH (0x0F00 0146) Name PIOD31 PIOD30 PIOD29 PIOD28 PIOD27 PIOD26 PIOD25 PIOD24 RTCRST After reset Name PIOD23 PIOD22 PIOD21 PIOD20 PIOD19 PIOD18 PIOD17 PIOD16 RTCRST After reset Name Function 15:0 PIOD(31:16) Specifies GPIO(31:16) pin output data. 1: High level 0: Low level This register reads and/or writes the GPIO(31:16) pins.
Page 261: Giuintstatl (0X0F00 0148)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.5 GIUINTSTATL (0x0F00 0148) Name INTS15 INTS13 INTS12 INTS11 INTS10 INTS9 INTS8 RTCRST After reset Name INTS7 INTS6 INTS5 INTS4 INTS3 INTS2 INTS1 INTS0 RTCRST After reset Name Function INTS15 Interrupt request to GPIO(15) pin. Cleared to 0 when 1 is written. 1: Interrupt occurred 0: No interrupt Reserved.
Page 262: Giuintstath (0X0F00 014A)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.6 GIUINTSTATH (0x0F00 014A) Name INTS31 INTS30 INTS29 INTS28 INTS27 INTS26 INTS25 INTS24 RTCRST After reset Name INTS23 INTS22 INTS21 INTS20 INTS19 INTS18 INTS17 INTS16 RTCRST After reset Name Function 15:0 INTS(31:16) Interrupt request to GPIO(31:16) pin. Cleared to 0 when 1 is written. 1: Interrupt occurred 0: No interrupt This register indicates the interrupt request status of the GPIO pins.
Page 263: Giuintenl (0X0F00 014C)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.7 GIUINTENL (0x0F00 014C) Name INTE15 INTE13 INTE12 INTE11 INTE10 INTE9 INTE8 RTCRST After reset Name INTE7 INTE6 INTE5 INTE4 INTE3 INTE2 INTE1 INTE0 RTCRST After reset Name Function INTE15 Interrupt enable to GPIO(15) pin. 1: Enable 0: Disable Reserved.
Page 264: Giuintenh (0X0F00 014E)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.8 GIUINTENH (0x0F00 014E) Name INTE31 INTE30 INTE29 INTE28 INTE27 INTE26 INTE25 INTE24 RTCRST After reset Name INTE23 INTE22 INTE21 INTE20 INTE19 INTE18 INTE17 INTE16 RTCRST After reset Name Function 15:0 INTE(31:16) Interrupt enable for GPIO(31:16) pins. 1: Enable 0: Disable This register sets the GPIO(31:16) pins to the interrupt enabled status.
Page 265: Giuinttypl (0X0F00 0150)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.9 GIUINTTYPL (0x0F00 0150) Name INTT15 INTT13 INTT12 INTT11 INTT10 INTT9 INTT8 RTCRST After reset Name INTT7 INTT6 INTT5 INTT4 INTT3 INTT2 INTT1 INTT0 RTCRST After reset Name Function INTT15 Interrupt request detection trigger to GPIO(15) pin. Reserved.
Page 266: Giuinttyph (0X0F00 0152)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.10 GIUINTTYPH (0x0F00 0152) Name INTT31 INTT30 INTT29 INTT28 INTT27 INTT26 INTT25 INTT24 RTCRST After reset Name INTT23 INTT22 INTT21 INTT20 INTT19 INTT18 INTT17 INTT16 RTCRST After reset Name Function 15:0 INTT(31:16) Interrupt request detection trigger 1: Edge 0: Level This register sets the trigger to detect an interrupt request for the GPIO(31:16) pins.
Page 267: Giuintalsell (0X0F00 0154)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.11 GIUINTALSELL (0x0F00 0154) Name INTL15 INTL13 INTL12 INTL11 INTL10 INTL9 INTL8 RTCRST After reset Name INTL7 INTL6 INTL5 INTL4 INTL3 INTL2 INTL1 INTL0 RTCRST After reset Name Function INTL15 Interrupt request detection level to GPIO(15) Reserved.
Page 268: Giuintalselh (0X0F00 0156)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.12 GIUINTALSELH (0x0F00 0156) Name INTL31 INTL30 INTL29 INTL28 INTL27 INTL26 INTL25 INTL24 RTCRST After reset Name INTL23 INTL22 INTL21 INTL20 INTL19 INTL18 INTL17 INTL16 RTCRST After reset Name Function 15:0 INTL(31:16) Interrupt request detection level 1: High level 0: Low level This register sets the level for the detection of interrupt requests to the GPIO(31:16) pins.
Page 269: Giuinthtsell (0X0F00 0158)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.13 GIUINTHTSELL (0x0F00 0158) Name INTH15 INTH13 INTH12 INTH11 INTH10 INTH9 INTH8 RTCRST After reset Name INTH7 INTH6 INTH5 INTH4 INTH3 INTH2 INTH1 INTH0 RTCRST After reset Name Function INTH15 Sets GPIO(15) pin interrupt request signal hold. Reserved.
Page 270: Giuinthtselh (0X0F00 015A)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.14 GIUINTHTSELH (0x0F00 015A) Name INTH31 INTH30 INTH29 INTH28 INTH27 INTH26 INTH25 INTH24 RTCRST After reset Name INTH23 INTH22 INTH21 INTH20 INTH19 INTH18 INTH17 INTH16 RTCRST After reset Name Function 15:0 INTH(31:16) Sets GPIO(31:16) pin interrupt request signal hold. 1: Hold 0: Through This register sets whether or not interrupt signals to the GPIO(31:16) pins should be held.
Page 271 CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) The relationship between the GPIO interrupt enable/disable and hold settings is as follows. Table 14-3. Correspondence Between Interrupt Mask and Interrupt Hold Interrupt Setting of Setting of GIUINTEN Hold in GIU Notation to ICU Trigger GIUINTHTSEL Register Register...
Page 272: Giupodaten (0X0F00 015C)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.15 GIUPODATEN (0x0F00 015C) Name RTCRST After reset Name PIOEN35 PIOEN34 PIOEN33 PIOEN32 RTCRST After reset Note Note Note Note Name Function 15:4 Reserved. Write 0. 0 is returned after a read. PIOEN(35:32) GPIO(35:32) pin output enable 1: Enable 0: Disable Note Value before reset is retained.
Page 273: Giupodatl (0X0F00 015E)
CHAPTER 14 GIU (GENERAL-PURPOSE I/O UNIT) 14.2.16 GIUPODATL (0x0F00 015E) Name RTCRST After reset Name PIOD35 PIOD34 PIOD33 PIOD32 RTCRST After reset Note Note Note Note Name Function 15:4 Reserved. Write 0. 0 is returned after a read. PIOD(35:32) GPIO(35:32) pin output data 1: High level 0: Low level Note Value before reset is retained.
Page 274: Chapter 15 Scu (Sysad Control Unit)
CHAPTER 15 SCU (SysAD CONTROL UNIT) 15.1 Outline The SCU performs bus arbitration so that multiple masters can be connected on the SysAD bus. The main specifications of the SCU are as follows: • Bus arbitration from multiple bus masters •...
Page 275: Timoutcntreg (0X0F00 1000)
CHAPTER 15 SCU (SysAD CONTROL UNIT) 15.2.1 TIMOUTCNTREG (0x0F00 1000) Name TIMOUT15 TIMOUT14 TIMOUT13 TIMOUT12 TIMOUT11 TIMOUT10 TIMOUT9 TIMOUT8 RTCRST After reset Name TIMOUT7 TIMOUT6 TIMOUT5 TIMOUT4 TIMOUT3 TIMOUT2 TIMOUT1 TIMOUTE RTCRST After reset Name Function 15:1 TIMOUT(15:1) Sets the value of the timeout detection. TIMOUTE Enables the timeout detection.
Page 276: Timoutcountreg (0X0F00 1002)
CHAPTER 15 SCU (SysAD CONTROL UNIT) 15.2.2 TIMOUTCOUNTREG (0x0F00 1002) Name TIMCNT15 TIMCNT14 TIMCNT13 TIMCNT12 TIMCNT11 TIMCNT10 TIMCNT9 TIMCNT8 RTCRST After reset Name TIMCNT7 TIMCNT6 TIMCNT5 TIMCNT4 TIMCNT3 TIMCNT2 TIMCNT1 TIMCNT0 RTCRST After reset Name Function 15:0 TIMCNT(15:0) Sets the value of a timeout counter. This counter synchronizes with VTClock.
Page 277: Errladdressreg (0X0F00 1004)
CHAPTER 15 SCU (SysAD CONTROL UNIT) 15.2.3 ERRLADDRESSREG (0x0F00 1004) Name ERRADR15 ERRADR14 ERRADR13 ERRADR12 ERRADR11 ERRADR10 ERRADR9 ERRADR8 RTCRST After reset Name ERRADR7 ERRADR6 ERRADR5 ERRADR4 ERRADR3 ERRADR2 ERRADR1 ERRADR0 RTCRST After reset Name Function 15:0 ERRADR(15:0) Holds the lower 16 bits of the physical address of the last CPU core timeout or accesses the reserved space.
Page 278: Scuintreg (0X0F00 1008)
CHAPTER 15 SCU (SysAD CONTROL UNIT) 15.2.5 SCUINTREG (0x0F00 1008) Name RTCRST After reset Name TIMOERR RSVERR RTCRST After reset Name Function 15:6 Reserved. Write 0. 0 is returned after a read. Reserved. Write 0. Value is undefined after a read. TIMOERR CPU core timeout error RSVERR...
Page 279: Notification Of Illegal Access
CHAPTER 15 SCU (SysAD CONTROL UNIT) 15.2.6 Notification of illegal access (1) Types of illegal access The V 4131 notifies the CPU core of the occurrence of an illegal access in the following cases using a non- maskable interrupt request (bus error exception) at reading or a maskable interrupt request (Int0) by SCUINTRREG at writing.
Page 280: Chapter 16 Sdramu (Sdram Control Unit)
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.1 General The SDRAMU is a unit that arbitrates between the SysAD bus and SDRAM. 16.2 Register Set The following table shows the SDRAMU registers. Table 16-1. SDRAM Registers Address Register Symbol Function 0x0F00 0400 SDRAMMODEREG SDRAM mode register 0x0F00 0402...
Page 281: Sdrammodereg (0X0F00 0400)
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.1 SDRAMMODEREG (0x0F00 0400) Name SCLK RTCRST After reset Name LTMODE2 LTMODE1 LTMODE0 RTCRST After reset Name Function SCLK Sets the SCLK output of the ADD25/SCLK pin. 1: SCLK is always output. 0: SCLK is output only when accessing SDRAM. 14:7 Reserved.
Page 282: Sdramcntreg (0X0F00 0402)
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.2 SDRAMCNTREG (0x0F00 0402) (1/2) Name TRC3 TRC2 TRC1 TRC0 RTCRST After reset Name TDAL2 TDAL1 TDAL0 TRCD2 TRCD1 TRCD0 RTCRST After reset Name Function 15:12 Reserved. Write 0. 0 is returned after a read. 11:8 TRC(3:0) Sets the minimum interval of the following cycles:...
Page 283 CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) (2/2) Name Function Sets the minimum interval of Bank active → Read/Read with auto-precharge/Write/ TRCD(2:0) write with auto-precharge 111: RFU 110: RFU 101: RFU 100: 4VTClock 011: 3VTClock 010: 2VTClock 001: RFU 000: RFU Set the value of TRC(3:0) according to TRC/TRC1 of the SDRAM to be used.
Page 284: Bcurfcntreg (0X0F00 0404)
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.3 BCURFCNTREG (0x0F00 0404) Name BRF13 BRF12 BRF11 BRF10 BRF9 BRF8 RTCRST After reset Name BRF7 BRF6 BRF5 BRF4 BRF3 BRF2 BRF1 BRF0 RTCRST After reset Name Function 15:14 Write 0. 0 is returned after a read. 13:0 BRF(13:0) DRAM refresh cycle count (VTClock count)
Page 285: Bcurfcountreg (0X0F00 0406)
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.4 BCURFCOUNTREG (0x0F00 0406) Name BRFC13 BRFC12 BRFC11 BRFC10 BRFC9 BRFC8 RTCRST After reset Name BRFC7 BRFC6 BRFC5 BRFC4 BRFC3 BRFC2 BRFC1 BRFC0 RTCRST After reset Name Function 15:14 Reserved. Write 0. 0 is returned after a read. 13:0 BRFC(13:0) Current DRAM refresh cycle count...
Page 286: Ramsizereg (0X0F00 0408)
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.5 RAMSIZEREG (0x0F00 0408) (1/2) Name SIZE32 SIZE31 SIZE30 SIZE22 SIZE21 SIZE20 RTCRST Note Note Note Note Note Note After reset Note Note Note Note Note Note Name SIZE12 SIZE11 SIZE10 SIZE02 SIZE01 SIZE00 RTCRST Note Note...
Page 287 CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) (2/2) Name Function Reserved. Write 0. 0 is returned after a read. SIZE1(2:0) Sets the RAM size of bank 1 in 16-bit mode or bank 1 in 32-bit mode. SIZE1(2:0) 16-bit mode 32-bit mode (MB) (MB) Reserved.
Page 288: Dram Connection
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.6 DRAM connection The following table shows an example of the connection between the V 4131 and DRAM. From the ADD pins (ADD(24:10)) of the V 4131 the row address (RAS signal) and column address (CAS signal) are output to DRAM (address multiplex mode supported) according to the RAS signal (RAS#) or CAS signal (CAS#).
Page 289: Sdram Interface
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.7 SDRAM interface The SCU supports bus operations for SDRAM. When accessing SDRAM in the V 4131 the following features are available: • The CAS latency can be selected from the two types of 2 and 3 (set using the SDRAMMODREG register). •...
Page 290 CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) (1) Single write cycle This section describes the timing when two successive 1-word write operations are performed. Commands for the first and second 1-word write are issued at <1> and <2>, and <3> and <4> in Figure 16-1, respectively. (a) First 1-word write <1>...
Page 291 CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) (2) Block write cycle This section describes the timing of the block write cycle. The V 4131 issues a write command with auto- precharge at the last bus cycle and performs precharge. For this operation the V 4122 issues a write command between the bank active command and write command with auto-precharge.
Page 292 CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) (3) Single read cycle This section describes the timing of the single read cycle. Figure 16-3. Single Read Cycle in 32-Bit Bus Mode (TRCD(2:0) = 010, TDAL(2:0) = 010, CAS Latency = 2) TRCD SCLK CKE(1:0) ADD(24:21), ADD(19:10)
Page 293 CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) (4) Block read cycle This section describes the timing of the block read cycle. The V 4131 issues a read command with auto- precharge at the last bus cycle and performs precharge. For this operation the V 4122 issues a read command between the bank active command and read command with auto-precharge.
Page 294: Refresh
CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) 16.2.8 Refresh The V 4131 supports CBR refresh and self-refresh. (1) CBR refresh Figure 16-5. CBR (Auto) Refresh SCLK ADD(24:21) ADD(19:10) ADD20 CS(1:0)# RAS# CAS# DQM(3:0)# SWR# DATA(31:0) CBR (Auto) refresh Preliminary User’s Manual U15350EJ2V0UM...
Page 295 CHAPTER 16 SDRAMU (SDRAM CONTROL UNIT) (2) Self-refresh Figure 16-6. Self-Refresh (Entry and Exit) SCLK (output) CKE(1:0) (output) ADD(24:21), ADD(19:10) (output) ADD20 (output) CS(1:0)# (output) RAS (output) CAS (output) DQM(3:0) (output) SWR# (output) DATA(31:0) (I/O) Self-refresh Self-refresh entry exit Preliminary User’s Manual U15350EJ2V0UM...
Page 296: Chapter 17 Pciu (Pci Control Unit)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.1 Overview The PCI control unit can connect the internal bus of the V 4131 to the PCI bus. The following describes the bridge specifications. 17.2 Specifications The features of the PCI interfacing of the PCI control unit are as follows: •...
Page 297: Reset Signals
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.3 Reset Signals The RST# signal can be used for PCI interface reset. The RST# signal is asserted by the following operation. • Reset by RTCRST# • Reset by RSTSWB • HALTimer shutdown • Software shutdown (HIBERNATE instruction) When the BMAS bit of the COMMANDREG register is set to 1, the RST# signal can be deasserted.
Page 298: Conversion Between Big Endian And Little Endian On Pci Bus In Big Endian Mode
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.5 Conversion Between Big Endian and Little Endian on PCI Bus in Big Endian Mode 17.5.1 When V 4131 is master Number of SysAD Data SysAD(2:0) SysAD(31:0) CBE (3:0) AD (31:0) Transfer Bytes (Internal Bus, Address) (Internal Bus, Data) (Data) 1 byte...
Page 299: When V R 4131 Is Target
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.5.2 When V 4131 is target Number of SysAD Data SysAD(2:0) SysAD(31:0) CBE (3:0) AD (31:0) Transfer Bytes (Internal Bus, Address) (Internal Bus, Data) (Data) 1 byte DCBA 1110 ABCD 1101 1011 0111 2 bytes CDAB 1100 ABCD...
Page 300: Transaction From Internal Bus To Pci (Pciu: Pci Master)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.6 Transaction from Internal Bus to PCI (PCIU: PCI Master) 17.6.1 Address conversion If an address of the internal bus space is output to the internal bus, the PCIU compares the higher bits of the address with the value preset in PCIMMAW1REG, PCIMMAW2REG, and PCIMIOAWREG.
Page 301: Remarks
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.6.4 Remarks Observe the following precautions for transactions between the internal bus and PCI. • When the memory is written or read, the lower 2 bits of the address sent from the internal bus side are fixed to 0 at the timing of converting to a PCI address.
Page 302: Transaction From Pci To Internal Bus (Pciu: Pci Target)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.7 Transaction from PCI to Internal Bus (PCIU: PCI Target) 17.7.1 Address conversion The PCIU transfers a transaction to the SDRAM space (0x07FF FFFF to 0x0000 0000) by receiving a memory cycle from other master devices on the PCI, as a PCI target. When transferring a transaction to the SDRAM space from the PCI bus, two windows are used to convert the address.
Page 303: Delayed Transaction
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.7.3 Delayed transaction Generally, when the PCIU operates as a target on the PCI bus, the PCIU can post memory write data or immediately transfers the memory read access cycle to the secondary bus by using its internal buffer. When posting is completed or the secondary bus cycle ends at this time, the bus cycle on the primary bus is completed.
Page 304: Interrupts
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.8 Interrupts PCIU has an interrupt output signal, INT_Z, which is asserted high and held high if any one of the interrupt sources listed in the table below occurs. The interrupt output and the status bit of the corresponding interrupt source are cleared if the CPU reads the INTCNTSTAREG register or writes 1 to the corresponding interrupt source clear bit.
Page 305: Internal Register Set
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9 Internal Register Set Table 17-5 lists the internal registers of the PCI. Table 17-5. PCI Internal Registers Address Register Symbols Function 0x0F00 0C00 PCIMMAW1REG PCI memory space address conversion register 1 for master transaction 0x0F00 0C04 PCIMMAW2REG PCI memory space address conversion register 2 for master transaction...
Page 306: Pcimmaw1Reg (0X0F00 0C00)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.1 PCIMMAW1REG (0x0F00 0C00) Name IBA31 IBA30 IBA29 IBA28 IBA27 IBA26 IBA25 IBA24 RTCRST After reset Name MSK6 MSK5 MSK4 MSK3 RTCRST After reset Name MSK2 MSK1 MSK0 WIN1EN RTCRST After reset Name PCIA31 PCIA30 PCIA29 PCIA28...
Page 307: Pcimmaw2Reg (0X0F00 0C04)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.2 PCIMMAW2REG (0x0F00 0C04) Name IBA31 IBA30 IBA29 IBA28 IBA27 IBA26 IBA25 IBA24 RTCRST After reset Name MSK6 MSK5 MSK4 MSK3 RTCRST After reset Name MSK2 MSK1 MSK0 WIN2EN RTCRST After reset Name PCIA31 PCIA30 PCIA29 PCIA28...
Page 308: Pcitaw1Reg (0X0F00 0C08)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.3 PCITAW1REG (0x0F00 0C08) Name RTCRST After reset Name MSK6 MSK5 MSK4 MSK3 RTCRST After reset Name MSK2 MSK1 MSK0 WIN1EN ITA10 ITA9 ITA8 RTCRST After reset Name ITA7 ITA6 ITA5 ITA4 ITA3 ITA2 ITA1 ITA0 RTCRST...
Page 309: Pcitaw2Reg (0X0F00 0C0C)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.4 PCITAW2REG (0x0F00 0C0C) Name RTCRST After reset Name MSK6 MSK5 MSK4 MSK3 RTCRST After reset Name MSK2 MSK1 MSK0 WIN2EN ITA10 ITA9 ITA8 RTCRST After reset Name ITA7 ITA6 ITA5 ITA4 ITA3 ITA2 ITA1 ITA0 RTCRST...
Page 310: Pcimioawreg (0X0F00 0C10)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.5 PCIMIOAWREG (0x0F00 0C10) Name IBA31 IBA30 IBA29 IBA28 IBA27 IBA26 IBA25 IBA24 RTCRST After reset Name MSK6 MSK5 MSK4 MSK3 RTCRST After reset Name MSK2 MSK1 MSK0 WIN1EN RTCRST After reset Name PCIIA31 PCIIA30 PCIIA29 PCIIA28...
Page 311: Pciconfdreg (0X0F00 0C14)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.6 PCICONFDREG (0x0F00 0C14) Name CONFD31 CONFD30 CONFD29 CONFD28 CONFD27 CONFD26 CONFD25 CONFD24 RTCRST After reset Name CONFD23 CONFD22 CONFD21 CONFD20 CONFD19 CONFD18 CONFD17 CONFD16 RTCRST After reset Name CONFD15 CONFD14 CONFD13 CONFD12 CONFD11 CONFD10 CONFD9 CONFD8...
Page 312: Pciconfareg (0X0F00 0C18)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.7 PCICONFAREG (0x0F00 0C18) Name CONFA31 CONFA30 CONFA29 CONFA28 CONFA27 CONFA26 CONFA25 CONFA24 RTCRST After reset Name CONFA23 CONFA22 CONFA21 CONFA20 CONFA19 CONFA18 CONFA17 CONFA16 RTCRST After reset Name CONFA15 CONFA14 CONFA13 CONFA12 CONFA11 CONFA10 CONFA9 CONFA8...
Page 313: Pcimailreg (0X0F00 0C1C)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.8 PCIMAILREG (0x0F00 0C1C) Name MBOX31 MBOX30 MBOX29 MBOX28 MBOX27 MBOX26 MBOX25 MBOX24 RTCRST After reset Name MBOX23 MBOX22 MBOX21 MBOX20 MBOX19 MBOX18 MBOX17 MBOX16 RTCRST After reset Name MBOX15 MBOX14 MBOX13 MBOX12 MBOX11 MBOX10 MBOX9 MBOX8...
Page 314: Buserradreg (0X0F00 0C24)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.9 BUSERRADREG (0x0F00 0C24) Name EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 RTCRST After reset Name EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 RTCRST After reset Name EA15 EA14 EA13 EA12 EA11 EA10 RTCRST After reset...
Page 315: Intcntstareg (0X0F00 0C28)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.10 INTCNTSTAREG (0x0F00 0C28) (1/3) Name MABTCLR TRDYCLR PARCLR MBCLR SERRCLR RTYCLR MABCLR TABCLR RTCRST After reset Name RTCRST After reset Name MABTMSK TRDYMSK PARMSK MBMSK SERRMSK RTYMSK MABMSK TABMSK RTCRST After reset Name IBAMABT TRDYRCH PCISERR...
Page 316 CHAPTER 17 PCIU (PCI CONTROL UNIT) (2/3) Name Function RTYCLR Clears PCI Retry Limit interrupt. 1: Cleared 0: Not MABCLR Clears PCI Master Abort interrupt. 1: Cleared 0: Not 23:16 Reserved. Write 0 to these bits. 0 is returned when these bits are read. TABCLR Clears PCI Target Abort interrupt.
Page 317 CHAPTER 17 PCIU (PCI CONTROL UNIT) (3/3) Name Function Accesses PCI Mailbox. 1: Accessed 0: Not accessed PCISERR Change of SERR#. 1: Asserted 0: Not asserted RTYRCH Retry Limit Reached. Indicates whether the PCIU has repeated retry the number of times set by RETVALREG when the PCIU operates as a PCI master.
Page 318: Pciexaccreg (0X0F00 0C2C)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.11 PCIEXACCREG (0x0F00 0C2C) Name RTCRST After reset Name RTCRST After reset Name RTCRST After reset Name UNLOCK EAREQ RTCRST After reset Name Function 31:2 Reserved. Write 0 to these bits. 0 is returned when these bits are read. UNLOCK Lock from device on PCI.
Page 319 CHAPTER 17 PCIU (PCI CONTROL UNIT) (1) If V 4131 acts as the PCI master When the V 4131 operates as the PCI master, first set the EAREQ bit of PCIEXACCREG to 1 to request a target for exclusive access. If the accessed target is ready to be locked in the next cycle, the target is locked to the PCIU.
Page 320: Pcirecontreg (0X0F00 0C30)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.12 PCIRECONTREG (0x0F00 0C30) Name RTCRST After reset Name RTCRST After reset Name RTCRST After reset Name RTRYCNT7 RTRYCNT6 RTRYCNT5 RTRYCNT4 RTRYCNT3 RTRYCNT2 RTRYCNT1 RTRYCNT0 RTCRST After reset Name Function 31:8 Reserved. Write 0 to these bits. 0 is returned when these bits are read. RTRYCNT(7:0) Retry count This register stores the result of counting the number of times the PCIU has generated a retry during a PCI bus...
Page 321: Pcienreg (0X0F00 0C34)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.13 PCIENREG (0x0F00 0C34) Name RTCRST After reset Name RTCRST After reset Name RTCRST After reset Name CONFIG_ DONE RTCRST After reset Name Function 31:3 Reserved. Write 0 to these bits. 0 is returned when these bits are read. CONFIG_DONE PCI Configuration Done 1: PCI transaction executed normally...
Page 322: Pciclkselreg (0X0F00 0C38)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.14 PCICLKSELREG (0x0F00 0C38) Name RTCRST After reset Name RTCRST After reset Name RTCRST After reset Name SEL_CLK1 SEL_CLK0 RTCRST After reset Name Function 31:2 Reserved. Write 0 to these bits. 0 is returned when these bits are read. SEL_CLK(1:0) Selects the PCI bus operation clock.
Page 323: Pcitrdyvreg (0X0F00 0C3C)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.15 PCITRDYVREG (0x0F00 0C3C) Name RTCRST After reset Name RTCRST After reset Name RTCRST After reset Name TRDYV7 TRDYV6 TRDYV5 TRDYV4 TRDYV3 TRDYV2 TRDYV1 TRDYV0 RTCRST After reset Name Function 31:8 Reserved. Write 0 to these bits. 0 is returned when these bits are read. TRDYV(7:0) Wait time limit period from asserting IRDY# to asserting TRDY#.
Page 324: Pciclkrunreg (0X0F00 0C60)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.9.16 PCICLKRUNREG (0x0F00 0C60) Name STOPEN RTCRST After reset Name CLKRUN RTCRST After reset Name Function STOPEN Indicates the result of arbitration requesting stoppage of the PCI clock by the CLKRUN signal. 1: PCI clock can be stopped. 0: PCI clock cannot be stopped 14:1 Reserved.
Page 325 CHAPTER 17 PCIU (PCI CONTROL UNIT) HIBERNATE: mfc0 t0,C0_SR t0,t0,0x1 xori t0,t0,0x1 mtc0 t0,C0_SR # Int. disable t0,0xab000000 # I/O register base address t1,0x0001 t1,0xC60(t0) # stopen = 0, clkrun = 1 chkloop: t2,0x60(t0) # load check bits t1,t2,chkloop t2,zero,NO_SLEEP mfc0 t0,C0_SR xori...
Page 326: Configuration Header Registers
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10 Configuration Header Registers The PCIU can access the PCI configuration space as a master. This PCIU has two one-word length registers: PCICONFAREG and PCICONFDREG. To access the PCI configuration space, first access PCICONFAREG of the internal registers and set the 32-bit PCI address of the configuration register to be accessed.
Page 327 CHAPTER 17 PCIU (PCI CONTROL UNIT) Table 17-6. PCI Configuration Header Registers Physical Address Abbreviation Function 0x0F00 0D00 VENDORIDREG Vendor ID register DEVICEIDREG Device ID register 0x0F00 0D04 COMMABDREG Command register that sets PCI interface STATUSREG Status register of PCI interface 0x0F00 0D08 REVIDREG Revision register of device...
Page 328: Vendoridreg, Deviceidreg (0X0F00 0D00)
31:16 DID(15:0) Device ID. 0x00DF for the V 4131. 15:0 VID(15:0) Vendor ID. 0x1033 for NEC. Among 32 bits starting at 0x0F00 0D00, bits 15:0 and 31:16 are used as the VENDORIDREG and DEVICEIDREG registers, respectively. Preliminary User’s Manual U15350EJ2V0UM...
Page 329: Commandreg, Statusreg (0X0F00 0D04)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.3 COMMANDREG, STATUSREG (0x0F00 0D04) (1/2) Name DEVSEL1 DEVSEL0 RTCRST After reset Name FBBC RTCRST After reset Name FBBE SERR_EN RTCRST After reset Name WAIT_CTL BMAS MEMEN IOEN RTCRST After reset Name Function Parity error detection 1: Detected 0: Not detected System error report...
Page 330 CHAPTER 17 PCIU (PCI CONTROL UNIT) (2/2) Name Function 26:25 DEVSEL(1:0) DEVSEL issue timing. The bits of the V 4131 are fixed to 01 (intermediate speed). Data parity error detection 1: PERR# is asserted or PERR# of other devices is detected. 0: No parity error FBBC High-speed back-to-back support...
Page 331: Revidreg, Classreg (0X0F00 0D08)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.4 REVIDREG, CLASSREG (0x0F00 0D08) Name BASECL7 BASECL6 BASECL5 BASECL4 BASECL3 BASECL2 BASECL1 BASECL0 RTCRST After reset Name SUBCL7 SUBCL6 SUBCL5 SUBCL4 SUBCL3 SUBCL2 SUBCL1 SUBCL0 RTCRST After reset Name PROG7 PROG6 PROG5 PROG4 PROG3 PROG2 PROG1...
Page 332: Cachelsreg, Lattimereg (0X0F00 0D0C)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.5 CACHELSREG, LATTIMEREG (0x0F00 0D0C) Name RTCRST After reset Name RTCRST After reset Name MLTIM7 MLTIM6 MLTIM5 MLTIM4 MLTIM3 MLTIM2 MLTIM1 MLTIM0 RTCRST After reset Name CLSIZ7 CLSIZ6 CLSIZ5 CLSIZ4 CLSIZ3 CLSIZ2 CLSIZ1 CLSIZ0 RTCRST After reset Name...
Page 333: Mailbareg (0X0F00 0D10)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.6 MAILBAREG (0x0F00 0D10) Name MBADD31 MBADD30 MBADD29 MBADD28 MBADD27 MBADD26 MBADD25 MBADD24 RTCRST After reset Name MBADD23 MBADD22 MBADD21 MBADD20 MBADD19 MBADD18 MBADD17 MBADD16 RTCRST After reset Name MBADD15 MBADD14 MBADD13 MBADD12 MBADD11 MBADD10 MBADD9 MBADD8...
Page 334: Pcimba1Reg (0X0F00 0D14)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.7 PCIMBA1REG (0x0F00 0D14) Name PMBA31 PMBA30 PMBA29 PMBA28 PMBA27 PMBA26 PMBA25 PMBA24 RTCRST After reset Name PMBA23 PMBA22 PMBA21 PMBA20 PMBA19 PMBA18 PMBA17 PMBA16 RTCRST After reset Name PMBA15 PMBA14 PMBA13 PMBA12 PMBA11 PMBA10 PMBA9 PMBA8...
Page 335: Pcimba2Reg (0X0F00 0D18)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.8 PCIMBA2REG (0x0F00 0D18) Name PMBA31 PMBA30 PMBA29 PMBA28 PMBA27 PMBA26 PMBA25 PMBA24 RTCRST After reset Name PMBA23 PMBA22 PMBA21 PMBA20 PMBA19 PMBA18 PMBA17 PMBA16 RTCRST After reset Name PMBA15 PMBA14 PMBA13 PMBA12 PMBA11 PMBA10 PMBA9 PMBA8...
Page 336: Intlinereg, Intpinreg (0X0F00 0D3C)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.9 INTLINEREG, INTPINREG (0x0F00 0D3C) Name RTCRST After reset Name RTCRST After reset Name INTPIN7 INTPIN6 INTPIN5 INTPIN4 INTPIN3 INTPIN2 INTPIN1 INTPIN0 RTCRST After reset Name INTLINE7 INTLINE6 INTLINE5 INTLINE4 INTLINE3 INTLINE2 INTLINE1 INTLINE0 R/WW RTCRST After reset...
Page 337: Retvalreg, Pciapcntreg (0X0F00 0D40)
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.10.10 RETVALREG, PCIAPCNTREG (0x0F00 0D40) Name TKYGNT PAPC1 PAPC0 RTCRST After reset Name RTCRST After reset Name RTYVAL7 RTYVAL6 RTYVAL5 RTYVAL4 RTYVAL3 RTYVAL2 RTYVAL1 RTYVAL0 RTCRST After reset Name RTCRST After reset Name Function 31:27 Reserved.
Page 338 CHAPTER 17 PCIU (PCI CONTROL UNIT) (PEQ0) priority algorithm. With each algorithm, preemption is enabled or disabled in a cycle (Take Away GNT). The PCIAPCNTREG register is used to specify the operation mode of the arbiter. The priority is changed every cycle. The PCIU provides the following three arbitration modes: Fair: Protocol that evenly allocates the priority assigned to the requests of all master devices 0 to 3.
Page 339: Transaction Transfer
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.11 Transaction Transfer This section explains the specifications related to the internal bus of the PCI and transaction transfer. 17.11.1 Transaction transfer path overview The type of transaction transfer between the PCI and internal bus and how to implement a transaction are described below.
Page 340: Transaction Transfer Case
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.11.2 Transaction transfer case The style of each transaction transfer shown in Table 17-7 is described below. (1) PCI → → → → Internal bus transaction (read) The read cycle from the PCI bus side is in the form of a delayed transaction. When the PCIU has received a read command for the internal bus on the PCI bus, it retains the address of the command, and completes that cycle with a retry.
Page 341: Abnormal Termination
CHAPTER 17 PCIU (PCI CONTROL UNIT) 17.12 Abnormal Termination This section explains the types of abnormal termination related to the PCIU. 17.12.1 From internal bus to PCI bus (1) Cause on PCI side The following cases may be listed as abnormal termination caused by the PCI bus for a PCI transaction from the internal bus.
Page 342: From Pci Bus To Internal Bus
CHAPTER 17 PCIU (PCI CONTROL UNIT) • Set the RTYRCH bit of the INTCNTSTAREG register to 1. • Write this PCI address to the BUSERRADREG register. (e) If target abort is received from the PCI target The cycle is terminated. Transfer is not retried. •...
Page 343: Chapter 18 Dsiu (Debug Serial Interface Unit)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.1 General The debug serial interface unit (DSIU) is a serial interface for debugging and supports transfer rates of up to 115 kbps. In addition to the DDIN and DDOUT input/output pins, the DSIU supports the DCTS# and DRTS# pins, which are used for flow control.
Page 344: Dsiurb (0X0F00 0820: Lcr7 = 0, Read)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.1 DSIURB (0x0F00 0820: LCR7 = 0, Read) Name RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RTCRST After reset Name Function RXD(7:0) Serial receive data This register stores receive data used in serial communications. To access this register, set the LCR7 bit of the DSIULC register to 0.
Page 345: Dsiuie (0X0F00 0821: Lcr7 = 0)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.4 DSIUIE (0x0F00 0821: LCR7 = 0) Name RTCRST After reset Name Function Reserved. Write 0. 0 is returned after read. Modem status interrupt 1: Enable 0: Disable Receive status interrupt 1: Enable 0: Disable Transmit holding register empty interrupt 1: Enable...
Page 346: Dsiudlm (0X0F00 0821: Lcr7 = 1)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.5 DSIUDLM (0x0F00 0821: LCR7 = 1) Name DLM7 DLM6 DLM5 DLM4 DLM3 DLM2 DLM1 DLM0 RTCRST After reset Name Function DLM(7:0) Baud rate divisor (higher byte) This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the lower DSIUDLL register are together handled as 16-bit data.
Page 347: Dsiuiid (0X0F00 0822: Read)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.6 DSIUIID (0x0F00 0822: Read) Name IIR7 IIR6 IIR3 IIR2 IIR1 IIR0 RTCRST After reset Name Function IIR(7:6) Becomes 11 when FCR0 = 1 Reserved. Write 0. 0 is returned after read. IIR3 Pending character timeout interrupt request (in FIFO mode) 1: No pending interrupt 0: Pending interrupt...
Page 348 CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) Table 18-3. Interrupt Set/Reset DSIUIID Register Interrupt Set/Reset Function Bit 3 Bit 2 Bit 1 Priority Level Interrupt Type Interrupt Source Interrupt Reset Control Note Highest (1st) Receive line Overrun error, parity error, framing Read line status status error, or break interrupt...
Page 349: Dsiufc (0X0F00 0822: Write)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.7 DSIUFC (0x0F00 0822: Write) Name FCR7 FCR6 FCR3 FCR2 FCR1 FCR0 RTCRST After reset Name Function FCR(7:6) Receive FIFO trigger level 11: 14 bytes 10: 8 bytes 01: 4 bytes 00: 0 bytes Reserved.
Page 350 CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) • FIFO interrupt modes When the receive FIFO is usable and receive interrupts are enabled, receive interrupts are generated as described below. <1> When the FIFO has reached the specified trigger level, a receive data existence interrupt request is generated to inform the CPU.
Page 351 CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) When the transmit FIFO is usable and transmit interrupts are enabled, transmit interrupt requests are generated as described below. <1> When the transmit FIFO becomes empty, a transmission hold register empty interrupt request is generated. This interrupt is cleared when a character is written to the transmission hold register (from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt), or when the DSIUIID register is read.
Page 352: Dsiulc (0X0F00 0823)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.8 DSIULC (0x0F00 0823) Name LCR7 LCR6 LCR5 LCR4 LCR3 LCR2 LCR1 LCR0 RTCRST After reset Name Function LCR7 Register switching at divisor latch access 1: Divisor latch access 0: Receive buffer, transmission hold register, interrupt enable register LCR6 Break control 1: Set break...
Page 353: Dsiumc (0X0F00 0824)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.9 DSIUMC (0x0F00 0824) Name MCR4 MCR3 MCR2 MCR1 MCR0 RTCRST After reset Name Function Reserved. Write 0. 0 is returned after read. MCR4 For diagnostic testing (local loopback) 1: Enable 0: Disable MCR3 OUT2 signal (internal) setting 1: Low level...
Page 354: Dsiuls (0X0F00 0825)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.10 DSIULS (0x0F00 0825) Name LSR7 LSR6 LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 RTCRST After reset Name Function LSR7 Error detection (in FIFO mode) 1: Parity error, framing error, or break is detected. 0: Normal LSR6 Transmit block empty...
Page 355 CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) The LSR7 bit is valid only in FIFO mode; it always indicates 0 in 16450 mode. The value of LSR4 becomes 1 when the spacing state (logical 0) is held longer than the time required for transmission of one word of receive data input (start bit + data bits + parity bit + stop bit).
Page 356: Dsiums (0X0F00 0826)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.11 DSIUMS (0x0F00 0826) Name MSR4 MSR0 RTCRST Undefined After reset Undefined Name Function Reserved. Write 0. 0 is returned after a read. MSR4 State of CTS# input 1: High level 0: Low level Reserved.
Page 357: Dsiusc (0X0F00 0827)
CHAPTER 18 DSIU (DEBUG SERIAL INTERFACE UNIT) 18.2.12 DSIUSC (0x0F00 0827) Name SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 RTCRST After reset Name Function SCR(7:0) General-purpose data This register is a readable/writable 8-bit register, and can be used freely by users. It does not affect control of the DSIU.
Page 358: Chapter 19 Led (Led Control Unit)
CHAPTER 19 LED (LED CONTROL UNIT) 19.1 General LEDs are switched on and off at a regular interval. That can be set by program. 19.2 Register Set The LED registers are listed below. Table 19-1. LED Registers Address Register Symbol Function 0x0F00 0180 LEDHTSREG...
Page 359: Ledhtsreg (0X0F00 0180)
CHAPTER 19 LED (LED CONTROL UNIT) 19.2.1 LEDHTSREG (0x0F00 0180) Name RTCRST After reset Name HTS4 HTS3 HTS2 HTS1 HTS0 RTCRST After reset Note Note Note Note Note Name Function 15:5 Reserved. Write 0. 0 is returned after a read. HTS(4:0) Sets LED on time.
Page 360: Ledltsreg (0X0F00 0182)
CHAPTER 19 LED (LED CONTROL UNIT) 19.2.2 LEDLTSREG (0x0F00 0182) Name RTCRST After reset Name LTS6 LTS5 LTS4 LTS3 LTS2 LTS1 LTS0 RTCRST After reset Note Note Note Note Note Note Note Name Function 15:7 Reserved. Write 0. 0 is returned after a read. LTS(6:0) Sets LED off time.
Page 361: Ledcntreg (0X0F00 0188)
CHAPTER 19 LED (LED CONTROL UNIT) 19.2.3 LEDCNTREG (0x0F00 0188) Name RTCRST After reset Name STOP ENABLE RTCRST After reset Note Note Name Function 15:2 Reserved. Write 0. 0 is returned after a read. LEDSTOP LED blink auto stop setting 1: Performs auto stop.
Page 362: Ledastcreg (0X0F00 018A)
CHAPTER 19 LED (LED CONTROL UNIT) 19.2.4 LEDASTCREG (0x0F00 018A) Name ASTC15 ASTC14 ASTC13 ASTC12 ASTC11 ASTC10 ASTC9 ASTC8 RTCRST After reset Name ASTC7 ASTC6 ASTC5 ASTC4 ASTC3 ASTC2 ASTC1 ASTC0 RTCRST After reset Name Function 15:0 ASTC(15:0) LED auto stop time blink count This register sets the number of ON/OFF times prior to the automatic stopping of LED activation.
Page 363: Ledintreg (0X0F00 018C)
CHAPTER 19 LED (LED CONTROL UNIT) 19.2.5 LEDINTREG (0x0F00 018C) Name RTCRST After reset Name LEDINT RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. LEDINT Auto stop interrupt request. Cleared to 0 when 1 is written. 1: Yes 0: No This register indicates when an auto stop interrupt request has occurred.
Page 364: Operation Flow
CHAPTER 19 LED (LED CONTROL UNIT) 19.3 Operation Flow Register initial setting Register 0x0010 (LED lighting time available) • LEDHTSREG: Note initial setting 0x0020 (LED OFF time available) • LEDLTSREG: 0x0000 • LEDHLTCLREG: 0x0000 • LEDHLTCHREG: • LEDCNTREG: 0x0002 LED blink 0x04B0 (Auto stop) •...
Page 365: Chapter 20 Siu (Serial Interface Unit)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.1 General The SIU is a serial interface supporting communication that conforms to the RS-232C standard and is equipped with two one-channel interfaces, one for transmission and one for reception. In addition, this unit can support the transfer rate of the infrared communication physical layer standard IrDA 1.1, SIR.
Page 366: Siurb (0X0F00 0800: Lcr7 = 0, Read)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.1 SIURB (0x0F00 0800: LCR7 = 0, Read) Name RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RTCRST After reset Name Function RXD(7:0) Serial receive data This register stores receive data used in serial communications. To access this register, set the LCR7 bit of the SIULC register to 0.
Page 367: Siuie (0X0F00 0801: Lcr7 = 0)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.4 SIUIE (0x0F00 0801: LCR7 = 0) Name RTCRST After reset Name Function Reserved. Write 0. 0 is returned after read. Modem status interrupt 1: Enable 0: Disable Receive status interrupt 1: Enable 0: Disable Transmission hold register empty interrupt 1: Enable 0: Disable...
Page 368: Siudlm (0X0F00 0801: Lcr7 = 1)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.5 SIUDLM (0x0F00 0801: LCR7 = 1) Name DLM7 DLM6 DLM5 DLM4 DLM3 DLM2 DLM1 DLM0 RTCRST After reset Name Function DLM(7:0) Baud rate divisor (higher byte) This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the lower SIUDLL register are together handled as 16-bit data.
Page 369: Siuiid (0X0F00 0802: Read)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.6 SIUIID (0x0F00 0802: Read) Name IIR7 IIR6 IIR3 IIR2 IIR1 IIR0 RTCRST After reset Name Function IIR(7:6) Becomes 11 when FCR0 = 1 Reserved. Write 0. 0 is returned after read. IIR3 Pending character timeout interrupt request (in FIFO mode) 1: No pending interrupt 0: Pending interrupt IIR(2:1)
Page 370 CHAPTER 20 SIU (SERIAL INTERFACE UNIT) Table 20-3. Interrupt Set/Reset SIUIID Register Interrupt Set/Reset Function Bit 3 Bit 2 Bit 1 Priority Level Interrupt Type Interrupt Source Interrupt Reset Control Note Highest Receive line Overrun error, parity error, framing Read line status (1st) status error, or break interrupt...
Page 371: Siufc (0X0F00 0802: Write)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.7 SIUFC (0x0F00 0802: Write) Name FCR7 FCR6 FCR3 FCR2 FCR1 FCR0 RTCRST After reset Name Function FCR(7:6) Receive FIFO trigger level 11: 14 bytes 10: 8 bytes 01: 4 bytes 00: 0 bytes Reserved.
Page 372 CHAPTER 20 SIU (SERIAL INTERFACE UNIT) • FIFO interrupt modes When the receive FIFO is usable and receive interrupts are enabled, receive interrupts are generated as described below. <1> When the FIFO has reached to the specified trigger level, a receive data existence interrupt request is generated to inform the CPU.
Page 373 CHAPTER 20 SIU (SERIAL INTERFACE UNIT) When the transmit FIFO is usable and transmit interrupts are enabled, transmit interrupt requests are generated as described below. <1> When the transmit FIFO becomes empty, a transmission hold register empty interrupt request is generated. This interrupt is cleared when a character is written to the transmission hold register (from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt), or when the SIUIID register is read.
Page 374: Siulc (0X0F00 0803)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.8 SIULC (0x0F00 0803) Name LCR7 LCR6 LCR5 LCR4 LCR3 LCR2 LCR1 LCR0 RTCRST After reset Name Function LCR7 Register switching at divisor latch access 1: Divisor latch access 0: Receive buffer, transmission hold register, interrupt enable register LCR6 Break control 1: Set break...
Page 375: Siumc (0X0F00 0804)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.9 SIUMC (0x0F00 0804) Name MCR4 MCR3 MCR2 MCR1 MCR0 RTCRST After reset Name Function Reserved. Write 0. 0 is returned after read. MCR4 For diagnostic testing (local loopback) 1: Enable 0: Disable MCR3 OUT2 signal (internal) setting 1: Low level 0: High level...
Page 376: Siuls (0X0F00 0805)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.10 SIULS (0x0F00 0805) Name LSR7 LSR6 LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 RTCRST After reset Name Function LSR7 Error detection (in FIFO mode) 1: Parity error, framing error, or break is detected. 0: Normal LSR6 Transmit block empty 1: No data in transmission hold register or transmit shift register...
Page 377 CHAPTER 20 SIU (SERIAL INTERFACE UNIT) The LSR7 bit is valid only in FIFO mode; it always indicates 0 in 16450 mode. The value of LSR4 becomes 1 when the spacing state (logical 0) is held longer than the time required for transmission of one word of receive data input (start bit + data bits + parity bit + stop bit).
Page 378: Siums (0X0F00 0806)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.11 SIUMS (0x0F00 0806) Name MSR7 MSR6 MSR5 MSR4 MSR3 MSR2 MSR1 MSR0 RTCRST Undefined Undefined Undefined Undefined After reset Undefined Undefined Undefined Undefined Name Function MSR7 State of DCD# signal 1: High level 0: Low level MSR6 State of RI signal (internal)
Page 379: Siusc (0X0F00 0807)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.12 SIUSC (0x0F00 0807) Name SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 RTCRST After reset Name Function SCR(7:0) General-purpose data This register is a readable/writable 8-bit register, and can be used freely by users. It does not affect control of the SIU.
Page 380: Siuirsel (0X0F00 0808)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.13 SIUIRSEL (0x0F00 0808) Name TMICMODE TMICTX IRMSEL1 IRMSEL0 IRUSESEL SIRSEL RTCRST After reset Name Function Reserved. Write 0. 0 is returned after read. TMICMODE If the emitter/receptor used is a TEMIC product, this bit is used. Mode setting of the emitter/receptor module by switching between low and high.
Page 381 CHAPTER 20 SIU (SERIAL INTERFACE UNIT) Figure 20-1. Example of Connection Between V 4131 and IrDA Module (a) HP model (b) TEMIC model IrDA IrDA 4131 4131 module module IRDIN RxDA IRDIN IRDOUT# IRDOUT# FIRDIN#/SEL FIRDIN#/SEL RxDB (c) SHARP model IrDA 4131 module...
Page 382: Siureset (0X0F00 0809)
CHAPTER 20 SIU (SERIAL INTERFACE UNIT) 20.2.14 SIURESET (0x0F00 0809) Name DSIU RESET RESET RTCRST After reset Name Function Reserved. Write 0. 0 is returned after a read. DSIURESET Resets DSIU. 1: Reset 0: Release SIURESET Resets SIU. 1: Reset 0: Release This register is used to reset the DSIU or the SIU forcibly.
Page 383: Chapter 21 Csi (Clocked Serial Control Unit)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.1 Outline The CSI, which is short for a clocked serial interface, is a synchronous serial interface. 21.2 Register Set The CSI registers are listed below. Table 21-1. CSI Registers Address Register Symbol Function 0x0F00 01A0 CSI_MODEREG...
Page 384: Csi_Modereg (0X0F00 01A0)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.1 CSI_MODEREG (0x0F00 01A0) Name CSIE TRMD AUTO CSOT RTCRST After reset Name Function CSIE Enables CSI unit operation. 1: Enable 0: Disable TRMD Sets transmit/receive. 1: Transmit and receive 0: Receive Sets data length. 1: 16 bits 0: 8 bits Sets communication direction.
Page 385: Csi_Clkselreg (0X0F00 01A1)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.2 CSI_CLKSELREG (0x0F00 01A1) Name CKS2 CKS1 CKS0 RTCRST After reset Name Function Reserved. Write 0. 0 is returned after a read. Selects clock phase. (See below.) Selects data phase. (See below) CKS(2:0) Selects clock.
Page 386: Csi_Sirbreg (0X0F00 01A2)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.3 CSI_SIRBREG (0x0F00 01A2) Name SIRB15 SIRB14 SIRB13 SIRB12 SIRB11 SIRB10 SIRB9 SIRB8 RTCRST After reset Name SIRB7 SIRB6 SIRB5 SIRB4 SIRB3 SIRB2 SIRB1 SIRB0 RTCRST After reset Name Function 15:0 SIRB(15:0) Receive data This is a 16-bit register for storing receive data.
Page 387: Csi_Sotbreg (0X0F00 01A4)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.4 CSI_SOTBREG (0x0F00 01A4) Name SOTB15 SOTB14 SOTB13 SOTB12 SOTB11 SOTB10 SOTB9 SOTB8 RTCRST After reset Name SOTB7 SOTB6 SOTB5 SOTB4 SOTB3 SOTB2 SOTB1 SOTB0 RTCRST After reset Name Function 15:0 SOTB(15:0) Transmit data This is a 16-bit register for storing transmit data.
Page 388: Csi_Sirbereg (0X0F00 01A6)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.5 CSI_SIRBEREG (0x0F00 01A6) Name SIRBE15 SIRBE14 SIRBE13 SIRBE12 SIRBE11 SIRBE10 SIRBE9 SIRBE8 RTCRST After reset Name SIRBE7 SIRBE6 SIRBE5 SIRBE4 SIRBE3 SIRBE2 SIRBE1 SIRBE0 RTCRST After reset Name Function 15:0 SIRBE(15:0) Receive data for read. This is a 16-bit register for storing receive data.
Page 389: Csi_Sotbfreg (0X0F00 01A8)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.6 CSI_SOTBFREG (0x0F00 01A8) Name SOTBF15 SOTBF14 SOTBF13 SOTBF12 SOTBF11 SOTBF10 SOTBF9 SOTBF8 RTCRST After reset Name SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 SOTBF1 SOTBF0 RTCRST After reset Name Function 15:0 SOTBF(15:0) First transmit data This is a 16-bit register for storing the first transmit data in sequential transfer mode (when the AUTO bit of the CSI_MODEREG register is 1).
Page 390: Csi_Sioreg (0X0F00 01Aa)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.7 CSI_SIOREG (0x0F00 01AA) Name SIO15 SIO14 SIO13 SIO12 SIO11 SIO10 SIO9 SIO8 RTCRST After reset Name SIO7 SIO6 SIO5 SIO4 SIO3 SIO2 SIO1 SIO0 RTCRST After reset Name Function 15:0 SIO(15:0) Shift data This is a 16-bit register for storing serial data converted from parallel data.
Page 391: Csi_Cntreg (0X0F00 01B0)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.8 CSI_CNTREG (0x0F00 01B0) (1/2) Name CSIRST T_TRGEN T_FIFOF T_FIFOE T_P1STP T_DMAEN RTCRST After reset Name SIO_V SIRB_V R_FULLS R_TRGEN R_FIFOF R_FIFOE R_P1STP R_DMAEN RTCRST After reset Name Function CSIRST Resets CSI unit 1: Reset state (default) 0: Normal state (0 is set when setting each register of CSI.) 14:13...
Page 392 CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) (2/2) Name Function R_TRGEN Enables receive halt when the receive FIFO reaches data set to R_TRG(2:0) of CSI_FIFOTRGREG. 1: Enable 0: Disable R_FIFOF Indicates the receive FIFO is FULL. 1: Full 0: Not full R_FIFOE Enables the use of receive FIFO.
Page 393: Csi_Intreg (0X0F00 01B2)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.9 CSI_INTREG (0x0F00 01B2) (1/2) Name CSIEND T_P2STP T_P1STP T_EMP RTCRST After reset Name R_P2STP R_P1STP R_OVER RTCRST After reset Name Function CSIEND Transmit and receive completion interrupt request This bit indicates that 1 data transmission or reception is completed. This bit is cleared to 0 when 1 is written.
Page 394 CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) (2/2) Name Function R_OVER CSICSB receive FIFO over interrupt request This bit is cleared to 0 when 1 is written. • R_TRGEN of the CSI_CNTREG register is 0: 1: Indicates that FIFO is Full on reception. 0: FIFO is not Full.
Page 395: Csi_Ififovreg (0X0F00 01B4)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.10 CSI_IFIFOVREG (0x0F00 01B4) (1/2) Name R_F7HV R_F7LV R_F6HV R_F6LV R_F5HV R_F5LV R_F4HV R_F4LV RTCRST After reset Name R_F3HV R_F3LV R_F2HV R_F2LV R_F1HV R_F1LV R_F0HV R_F0LV RTCRST After reset Name Function R_F7HV Indicates that the higher receive FIFO7 is valid. This bit is cleared when 0 is written. 1: Valid 0: Invalid R_F7LV...
Page 396 CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) (2/2) Name Function R_F2HV Indicates that the higher receive FIFO2 is valid. This bit is cleared when 0 is written. 1: Valid 0: Invalid R_F2LV Indicates that the lower receive FIFO2 is valid. This bit is cleared when 0 is written. 1: Valid 0: Invalid R_F1HV...
Page 397: Csi_Ofifovreg (0X0F00 01B6)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.11 CSI_OFIFOVREG (0x0F00 01B6) (1/2) Name T_F7HV T_F7LV T_F6HV T_F6LV T_F5HV T_F5LV T_F4HV T_F4LV RTCRST After reset Name T_F3HV T_F3LV T_F2HV T_F2LV T_F1HV T_F1LV T_F0HV T_F0LV RTCRST After reset Name Function T_F7HV Indicates that the higher transmit FIFO7 is valid. This bit is cleared when 0 is written. 1: Valid 0: Invalid T_F7LV...
Page 398 CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) (2/2) Name Function T_F2HV Indicates that the higher transmit FIFO2 is valid. This bit is cleared when 0 is written. 1: Valid 0: Invalid T_F2LV Indicates that the lower transmit FIFO2 is valid. This bit is cleared when 0 is written. 1: Valid 0: Invalid T_F1HV...
Page 399: Csi_Ififoreg (0X0F00 01B8)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.12 CSI_IFIFOREG (0x0F00 01B8) Name IFIFO15 IFIFO14 IFIFO13 IFIFO12 IFIFO11 IFIFO10 IFIFO9 IFIFO8 RTCRST After reset Name IFIFO7 IFIFO6 IFIFO5 IFIFO4 IFIFO3 IFIFO2 IFIFO1 IFIFO0 RTCRST After reset Name Function 15:0 IFIFO(15:0) Receive FIFO buffer data This is a window register for reading data from the receive FIFO buffers.
Page 400: Csi_Ofiforeg (0X0F00 01Ba)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.13 CSI_OFIFOREG (0x0F00 01BA) Name OFIFO15 OFIFO14 OFIFO13 OFIFO12 OFIFO11 OFIFO10 OFIFO9 OFIFO8 RTCRST After reset Name OFIFO7 OFIFO6 OFIFO5 OFIFO4 OFIFO3 OFIFO2 OFIFO1 OFIFO0 RTCRST After reset Name Function 15:0 OFIFO(15:0) Transmit FIFO register data This is a window register for writing data to the transmit FIFO buffers.
Page 401: Csi_Fifotrgreg (0X0F00 01Bc)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.2.14 CSI_FIFOTRGREG (0x0F00 01BC) Name T_TRG2 T_TRG1 T_TRG0 RTCRST After reset Name R_TRG2 R_TRG1 R_TRG0 RTCRST After reset Name Function 15:11 Reserved. Write 0. 0 is returned after a read. 10:8 T_TRG(2:0) Stops transfer of transmit FIFO 111: Halts after transmission of 8 ×...
Page 402: Clock Phase Selection Timing Chart
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.3 Clock Phase Selection Timing Chart • 8-bit data length (CCL = 0) • MSB first mode (DIR = 0) • When CKP = 0, DAP = 0 SECLK SOUT • When CKP = 1, DAP = 0 SECLK SOUT •...
Page 403: Details Concerning Single Transfer Mode
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.4 Details Concerning Single Transfer Mode Single transfer mode is entered when the AUTO bit of the CSI_MODEREG register is cleared. The method for starting transmission/reception differs depending on the state of the CSI_MODEREG register’s TRMD bit.
Page 404: Single Transfer Mode Timing (16-Bit Transfer)
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.4.2 Single transfer mode timing (16-bit transfer) When CSI_MODEREG’s TRMD = 1, CCL = 1, DIR = 1, AUTO = 0, and CSI_CLKSELREG’s CKP = 0: When transmit data is written to the CSI_SOTBREG register, after half a clock (SECLK), the SECLK clock is output in 16-clock units.
Page 405: Details Concerning Sequential Transfer Mode
CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) 21.5 Details Concerning Sequential Transfer Mode Sequential transfer mode is entered when the AUTO bit of the CSI_MODEREG register is set. Both the transmit/receive FIFO buffers and transmit/receive DMA can be used in sequential transfer mode. 21.5.1 When transmit/receive FIFO is not used When the T_FIFOE or R_FIFOE bit of the CSI_CNTREG register is cleared in sequential transfer mode, transmit/receive data must be exchanged in synchronization with the transfer cycle.
Page 406 CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) (b) When TRMD of CSI_MODEREG is 1: Transmission/reception is started by writing the data to be transmitted to the CSI_OFIFOREG register. The CSOT bit of CSI_MODEREG register becomes 1 at the start of transfer. When the T_TRGEN bit of the CSI_CNTREG register is 0 following the start of transmission, transmission continues as long as data remains in the transmit FIFO buffers.
Page 407 CHAPTER 21 CSI (CLOCKED SERIAL CONTROL UNIT) If reception is terminated by an interrupt that occurred during reception, it will not resume even if the interrupt is cancelled. Preliminary User’s Manual U15350EJ2V0UM...
Page 408: Chapter 22 Fir (Fast Irda Interface Unit)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.1 General This unit supports the FIR (Fast SIR) transfer rate; 0.576 Mbps, 1.152 Mbps, and 4 Mbps in the IrDA 1.1 high- speed infrared communication physical layer standard. SIR (up to 1.152 kbps) is not supported. 22.2 Register Set The FIR registers are listed below.
Page 409: Frstr (0X0F00 0840)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.1 FRSTR (0x0F00 0840) Name RTCRST After reset Name FRST RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. FRST FIR reset. Write 0 when releasing reset. 1: Reset 0: Normal Preliminary User’s Manual U15350EJ2V0UM...
Page 410: Dpintr (0X0F00 0842)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.2 DPINTR (0x0F00 0842) Name RTCRST After reset Name FDPINT5 FDPINT4 FDPINT3 FDPINT2 FDPINT1 RTCRST After reset Name Function 15:5 Reserved. Write 0. 0 is returned after a read. FDPINT5 FIR interrupt 1: Generated 0: Normal FDPINT4 Receive DMA 2-page interrupt request.
Page 411: Dpcntr (0X0F00 0844)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.3 DPCNTR (0x0F00 0844) Name RTCRST After reset Name FDPCNT RTCRST After reset Name Function 15:1 Reserved. Write 0. 0 is returned after a read. FDPCNT Sets whether or not to stop the DMA transfer at the first page. 1: 1-page transfer 0: 2-page transfer Cautions 1.
Page 412: Tdr (0X0F00 0850)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.4 TDR (0x0F00 0850) Name RTCRST After reset Name TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. TDR(7:0) Transmit data FIFO This register is used to store the address to which data is written to the transmit data store FIFO.
Page 413: Rdr (0X0F00 0852)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.5 RDR (0x0F00 0852) Name RTCRST After reset Name RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. RDR(7:0) Receive data FIFO This register is used to store the address from which data is read from the receive data store FIFO.
Page 414: Imr (0X0F00 0854)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.6 IMR (0x0F00 0854) Name RTCRST After reset Name IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. IMR(7:0) These bits are used to enable/disable interrupt output.
Page 415: Fsr (0X0F00 0856)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.7 FSR (0x0F00 0856) Name RTCRST After reset Name RX_TH1 RX_TH0 TX_TH1 TX_TH0 F_SIZE TXF_CLR RXF_CLR TX_STOP RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. RX_TH(1:0) Specifies the receive FIFO’s threshold.
Page 416 CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) Cautions 1. During transmission/reception, the contents of bits 7 to 3 of the FSR register must not be changed (refresh is possible). 2. The data in the FIFO is not cleared even if the TXF_CLR or RXF_CLR bit is set (clearing the pointer).
Page 417: Irsr1 (0X0F00 0858)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.8 IRSR1 (0x0F00 0858) Name RTCRST After reset Name IRDA_EN IRDA_MD MIR_MD RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. IRDA_EN FIR operation enable 1: Enable 0: Disable Reserved.
Page 418: Crcsr (0X0F00 085C)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.9 CRCSR (0x0F00 085C) Name RTCRST After reset Name TX_EN RX_EN 4PPM_DIS DPLL_DIS NON_CRC CRC_INV DATA_INV RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. TX_EN Masking enable of transmit start enable flag. 1: Enable 0: Disable RX_EN...
Page 419 CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) The TX_EN bit is used to set whether to mask sequence transition to the transmission enable state entered by writing the TXFL register. The RX_EN bit is used to set whether to release masking of the receive line and to enable data sampling and receive clock generation.
Page 420: Fircr (0X0F00 085E)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.10 FIRCR (0x0F00 085E) Name RTCRST After reset Name PA_LEN2 PA_LEN1 PA_LEN0 W_PULSE1 W_PULSE0 F_WIDTH2 F_WIDTH1 F_WIDTH0 RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. PA_LEN(2:0) Specifies the number of PA (preamble).
Page 421: Mircr (0X0F00 0860)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.11 MIRCR (0x0F00 0860) Name RTCRST After reset Name STA_LEN2 STA_LEN1 STA_LEN0 M_WIDTH4 M_WIDTH3 M_WIDTH2 M_WIDTH1 M_WIDTH0 RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. STA_LEN(2:0) Specifies the number of STA (start flag).
Page 422: Dmacr (0X0F00 0862)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.12 DMACR (0x0F00 0862) Name RTCRST After reset Name ACES_MD TRANS_MD DEMAND2 DEMAND1 DEMAND0 RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. ACES_MD Selects the access mode. Write 0 when writing. 0 is returned after a read. TRANS_MD Specifies the transfer direction.
Page 423: Dmaer (0X0F00 0864)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.13 DMAER (0x0F00 0864) Name RTCRST After reset Name DMA_BUSY DMA_EN RTCRST After reset Name Function 15:2 Reserved. Write 0. 0 is returned after a read. DMA_BUSY DMA busy status 1: DMA operation in progress 0: DMA operation not in progress DMA_EN DMA operation enable trigger...
Page 424: Txir (0X0F00 0866)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.14 TXIR (0x0F00 0866) Name RTCRST After reset Name TX_BUSY LAST_TFL TX_TH_OV TXF_UNDR TXF_FULL TXF_EMP RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. TX_BUSY Transmission busy 0: Not in transmission 1: In transmission Reserved.
Page 425: Rxir (0X0F00 0868)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.15 RXIR (0x0F00 0868) Name RTCRST After reset Name RX_BUSY END_DATA LAST_RFL RX_TH_O RXF_FULL RXF_EMP RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. RX_BUSY Reception busy 0: Reception in progress 1: Reception no in progress END_DATA...
Page 426: Ifr (0X0F00 086A)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.16 IFR (0x0F00 086A) Name RTCRST After reset Name TX_ABORT TX_ERR RX_VALID DMA_END RX_END TX_END TX_WR_RQ RX_RD_RQ RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. TX_ABORT Abort frame transmission end interrupt 0: Normal 1: Generated...
Page 427 CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) This register indicates the generation of FIR interrupt requests. The TX_ABORT bit is set when the abort frame is transmitted and the following frame’s transfer reservation is cancelled. The TX_ERR bit is set when a transmission error (such as a forcible stop) occurs. The RX_VALID bit is set when the last data of the frame is read from the receive FIFO and the received status becomes valid.
Page 428: Rxsts (0X0F00 086C)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.17 RXSTS (0x0F00 086C) Name RTCRST After reset Name VALID RXF_OV CRC_ERR ABORT MRXF_OV RTCRST After reset Name Function 15:8 Reserved. Write 0. 0 is returned after a read. VALID Receive data read status 0: Not completed 1: Completed Reserved.
Page 429 CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) (1) Write (bits 4 to 1) The receive status is written to these bits at the same timing of writing data to the receive frame length register. This register shares the write pointer with the receive frame length register. (2) Write (bit 7) This bit is set to 1 when the data of receive frame size is read from the FIFO.
Page 430: Txfl (0X0F00 086E)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.18 TXFL (0x0F00 086E) Name TXFL12 TXFL11 TXFL10 TXFL9 TXFL8 RTCRST After reset Name TXFL7 TXFL6 TXFL5 TXFL4 TXFL3 TXFL2 TXFL1 TXFL0 RTCRST After reset Name Function 15:13 Reserved. Write 0. 0 is returned after a read. 12:0 TXFL(12:0) Transmit frame size.
Page 431: Mrxf (0X0F00 0870)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.19 MRXF (0x0F00 0870) Name MRXF12 MRXF11 MRXF10 MRXF9 MRXF8 RTCRST After reset Name MRXF7 MRXF6 MRXF5 MRXF4 MRXF3 MRXF2 MRXF1 MRXF0 RTCRST After reset Name Function 15:13 Reserved. Write 0 to these bits. 0 is returned after a read. 12:0 MRXF(12:0) Specifies receivable maximum frame size.
Page 432: Rxfl (0X0F00 0874)
CHAPTER 22 FIR (FAST IrDA INTERFACE UNIT) 22.2.20 RXFL (0x0F00 0874) Name RXFL12 RXFL11 RXFL10 RXFL9 RXFL8 RTCRST After reset Name RXFL7 RXFL6 RXFL5 RXFL4 RXFL3 RXFL2 RXFL1 RXFL0 RTCRST After reset Name Function 15:13 Reserved. Write 0. 0 is returned after a read. 12:0 RXFL(12:0) Receive frame size.
Page 433: Chapter 23 Cp0 Hazards
CHAPTER 23 CP0 HAZARDS The V 4130 CPU core avoids contention of its internal resources by causing a pipeline interlock in cases when the contents of the destination register of an instruction are used as a source in the succeeding instruction. Therefore, instructions such as NOP must not be inserted between instructions.
Page 434 CHAPTER 23 CP0 HAZARDS Table 23-1. CP0 Hazards Operation Source Destination Source Name No. of Cycles Destination Name No. of Cycles MTC0 cpr rd MFC0 cpr rd TLBR Index, TLB PageMask, EntryHi, EntryLo0, EntryLo1 TLBWI Index or Random, PageMask, TLBWR EntryHi, EntryLo0, EntryLo1 TLBP PageMask, EntryHi...
Page 435 CHAPTER 23 CP0 HAZARDS Caution If the setting of the K0 bit in the config register is changed to uncached mode by MTC0, the accessed memory area is switched to an uncached one at the instruction fetch of the second instruction after MTC0.
Page 436 CHAPTER 23 CP0 HAZARDS (8) CACHE index store tag Source: The confirmation of registers containing information necessary for executing this instruction. (9) Coprocessor usable test Source: The confirmation of modes set by the bits of the CP0 registers in the “Source” column. Examples 1.
Page 437 CHAPTER 23 CP0 HAZARDS Table 23-2 indicates examples of calculation. Table 23-2. Calculation Example of CP0 Hazard and Number of Instructions Inserted Destination Source Contending Number of Formula Internal Instructions Resource Inserted TLBWR/TLBWI TLBP TLB Entry 6 – (3 + 1) TLBWR/TLBWI Load or store using newly modified TLB TLB Entry...
Page 438: Chapter 24 Pll Passive Components
CHAPTER 24 PLL PASSIVE COMPONENTS Several passive components need to be connected externally for proper operation of the V 4131. A connection example of the PLL passive components is shown in Figure 24-1. Figure 24-1. Example of Connection of PLL Passive Components 4131 GNDP Remarks 1.
Page 439: Appendix A Differences Between Revision 1.2 And Revision 2.0 Or Later
APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER This appendix describes the pins and functions that have been added to or eliminated from revision 2.0 and subsequent revisions of the V 4131. These descriptions are not applicable if revision 1.2 or an earlier revision is used.
Page 440 APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER Table A-2. Debug Interface Signals (1/2) Signal Name Function JTCK JTAG Clock This is the N-Wire clock input. JTMS JTAG Mode Select This is the N-Wire serial transfer mode selection signal. JTDI/RMODE# JTAG Data Input / Reset Mode This is the RMODE# and JTDI alternate-function pin.
Page 441: Pin Status
APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER Table A-2. Debug Interface Signals (2/2) Signal Name Function HLDAK#/ N-Wire Enable / Hold Acknowledge NWIREEN The function differs depending on the operation status. • After RTC reset (input) NWIREEN: This is the HALTimer shutdown function control signal and N-Wire use enable signal.
Page 442: Functions Added To/Deleted From Revision 2.0
APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER (2) Pin handling and I/O circuit types Table A-4. Pin Connections and I/O Circuit Types Pin Name Pin Handling Recommended Handling Drive I/O Circuit When Unused Performance Type − BKTGIO# Note Connect to V...
Page 443: Elimination Of Mmu Disable Mode
APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER (2) Connection circuit example A sample connection circuit using the 8830E-026-170S connector made by KEL Corporation is shown below. Figure A-1. Debug Tool Connection Circuit Example 3.3 V 3.3 V 4131 8830E-026-170S TRCCLK...
Page 444: Functions Added To Revision 2.1
APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER A.3 Functions Added to Revision 2.1 A.3.1 Addition of PCIU internal register The PCIU internal register shown in Table A-5 has been added to V 4131 revision 2.1 and later. Table A-5.
Page 445 APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER (a) When V 4131 = master (BYTESWAP = 1/0) Number of SysAD(2:0) (Internal SysAD(31:0) (Internal CBE(3:0) AD(31:0) (Data) SysAD Data Bus, Address) Bus, Address) Transfer Bytes 1 byte ABCD 1110 DCBA 1101...
Page 446 APPENDIX A DIFFERENCES BETWEEN REVISION 1.2 AND REVISION 2.0 OR LATER (c) V 4131 = target (BYTESWAP = 0) Number of SysAD(2:0) SysAD(31:0) CBE(3:0) AD(31:0) (Data) SysAD Data (Internal Bus, (Internal Bus, Transfer Bytes Address) Data) 1 byte DCBA 1110 ABCD 1101 1011...
Page 447: Appendix B Index
APPENDIX B INDEX Config register ............110 Connecting address pins........144 Abnormal termination..........341 Context register ............98 Access size............147 CONTROLREG ............180 Address conversion ........300, 302 Coprocessor 0 (CP0)..........36 Addressing............... 41 Count register............101 CP0 hazards............433 CP0 registers............45 BadVAddr register ..........101 CP0 REGISTERS.............95 BASSCNTHREG............
Page 448 APPENDIX B INDEX DCU registers ..........29, 173 ETIMELREG ............238 DEBUG serial interface unit (SIU)......343 ETIMEMREG ............238 DMA address unit (DMAAU) ........160 EXCEPTION PROCESSING ........86 DMA Control unit (DCU)......... 173 Exception program counter (EPC) register.... 108 DMA priority levels ..........
Page 449 APPENDIX B INDEX GIUPODATL ............273 Load mitigation buffer..........151 Local loopback ..........353, 375 HALTimer shutdown ........125, 215 Hibernate mode ..........131, 223 MAILBAREG ............333 MBCUINTREG ............212 MCSIINTREG ............210 I/O registers ............. 28 MDSIUINTREG ............196 ICU..............26, 187 MEMORY MANAGEMENT SYSTEM .......74 ICU registers............
Page 450 APPENDIX B INDEX PCIMMAW1REG............ 306 ROM interface ............148 PCIMMAW2REG............ 307 ROMSIZEREG............136 PCIRECONTREG ..........320 ROMSPEEDREG ..........138 PCITAW1REG ............308 RSTSW..............122 PCITAW2REG ............309 RSTSW reset............214 PCITRDYVREG ............. 323 RTC ..............26, 236 PCIU ..............296 RTC Long timer .............
Page 451 APPENDIX B INDEX SIUSC..............379 TClock counter ............236 SIUTH ..............366 TDR ................412 Soft reset ............... 129 TDREG..............178 SOFTINTREG............198 TIMOUTCNTREG...........275 Software shutdown ........123, 215 TIMOUTCOUNTREG ..........276 Standby mode..........130, 223 TLB................47 Startup factors ..........216, 224 Translation lookaside buffer (TLB) ......47 Status after reset ...........
Page 452 [MEMO] Preliminary User’s Manual U15350EJ2V0UM...
Page 453 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.