Related Manuals for NEC VR4133
Summary of Contents for NEC VR4133
-
Page 1: Operating Precautions
Customer Notification 4133 64-bit Microprocessor Operating Precautions µPD30133F3-266-GA3-A Document No. TPS-HE-B-6009-4 Date Published: June 2004 NEC Electronics (Europe) GmbH... - Page 2 The customer agrees to indemnify NEC against and hold NEC harmless from any and all consequences of any and all claims, suits, actions or demands asserted against NEC made by a third party for damages caused by one or more of the items listed in the enclosed table of content of this customer notification for PRODUCT(S) supplied after the date of publication.
- Page 3 Table of Operating Precautions ... 4 Description of Operating Precautions... 5 Valid Specification... 10 Revision History ... 11 Table of Contents Customer Notification...
-
Page 4: (A) Table Of Operating Precautions
(A) Table of Operating Precautions Outline Simultaneous locking of cache lines with the same index Reception of non IEEE802.3 conformant packages Register content in Ether0/1 blocks Read access from external PCI master Write access to external I/O area Branch delay slot of JAL(X) instruction in MIPS16 mode Disconnect at the end of PCI burst cycle Ethernet: receive short packet... -
Page 5: (B) Description Of Operating Precautions
(B) Description of Operating Precautions No. 1 Simultaneous locking of cache lines with the same index (Specification change notice) Details Simultaneous locking of two cache lines with the same index (i.e. in both cache ways) is prohibited. No. 2 Reception of non IEEE802.3 conformant packages (Specification change notice) Details In case of the reception of a non-IEEE802.3 conformant 18-Byte length Ethernet packet, the... - Page 6 No. 5 Write access to external I/O area (Direction of usage) Details A write cycle to external I/O or Flash area after • a CPU read/write access to a BCU-managed registers • or a CPU I/O read after a bus hold •...
- Page 7 Disconnect at the end of PCI burst cycle (Specification change notice) Details The last transfer of a PCI burst cycle is regarded as a disconnect cycle by VR4133, if STOP# and TRDY# are both asserted during the last-but-one data cycle, as shown in the following figure: PCLK...
- Page 8 No. 9 Ethernet: excessive data transfer into memory (Direction of usage) Details If two or more packets are received continuously, excessive data may be written at the end of a packet. The length of excessive data depends on the value of the DRBS0/1 bits of register RCV_CFGR0/1 (0x0f00 1618 / 0x0f00 1918) and becomes up to [burst length -1].
- Page 9 XX-Bit=0. LL instruction, SC instruction LLD instruction (64-bit mode only) and SCD instruction (64-bit mode only) do not cause a reserved instruction exception in any case. This description will be added within the documentation of the VR4133. No. 14 PCI DMA function...
-
Page 10: (C) Valid Specification
(C) Valid Specification Item Date published Document No. April 2004 U16551EJ2V0DS00 February 2004 U16620EJ3V0UM00 Operating Precautions for V 4133 Document Title 4133 Preliminary Data Sheet 4133 User Manual Customer Notification... -
Page 11: (D) Revision History
(D) Revision History Item Date published Document No. October 2003 TPS-HE-B-6009-1 January 2004 TPS-HE-B-6009-2 May 2004 TPS-HE-B-6009-3 June 2004 TPS-HE-B-6009-4 Operating Precautions for V 4133 Comment release Added item 8 to 12 Modified item 10 Added item 13 and 14 Customer Notification...