NEC startWARE-GHS-VR4131 Preliminary User's Manual
NEC startWARE-GHS-VR4131 Preliminary User's Manual

NEC startWARE-GHS-VR4131 Preliminary User's Manual

Starter kit vr4131
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Preliminary User's Manual
startWARE-GHS-V
4131
R
Starter Kit V
4131
R
Document No. U16417EE1V0UM00
Date Published February 2003
 NEC Corporation 2003
Printed in Germany

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Summary of Contents for NEC startWARE-GHS-VR4131

  • Page 1 Preliminary User’s Manual startWARE-GHS-V 4131 Starter Kit V 4131 Document No. U16417EE1V0UM00 Date Published February 2003  NEC Corporation 2003 Printed in Germany...
  • Page 2 The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC. NEC assumes no liability for infringement of patents or copyrights of third parties by or arising from use of a product described herein.
  • Page 3 NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
  • Page 4: Regional Information

    Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 5: Preface

    Preface Readers This manual is intended for users who want to understand the functions of the startWARE-GHS-V 4131 Starter Kit. Purpose This manual presents the hardware manual of startWARE-GHS-V 4131 Starter Kit.. Organization This system specification describes the following sections: •...
  • Page 6 Preliminary User’s Manual U16417EE1V0UM00...
  • Page 7: Table Of Contents

    Table of Contents Preface ............5 Chapter 1 Introduction.
  • Page 8 S-Boot Startup Message......... . . 62 5.2.3 Flash Monitor of startWARE-GHS-VR4131 ......63 5.2.4 FLASH Options .
  • Page 9 FPGA Block Diagram - I/O Circuits ................18 Figure 3-2: FPGA State Diagram – Power on Logic ..............19 Figure 3-3: startWARE-GHS-VR4131 address map for kseg1 (unmapped, uncached) ....20 Figure 4-1: Jumper positions ......................28 Figure 4-2: DIP switch setting for SW1 and SW2 ................29 Figure 4-3: Power supply connectors (board front view) ...............
  • Page 10 Preliminary User’s Manual U16417EE1V0UM00...
  • Page 11 List of Tables Table 4-1: VR4131 GPIO pin usage ....................21 Table 4-2: Example for default jumper setting marking ..............22 Table 4-3: Pipeline clock setting for VR4131................... 22 Table 4-4: Jumper positions for pipeline clock setting ..............23 Table 4-5: Jumper positions for endianness setting ................
  • Page 12 Preliminary User’s Manual U16417EE1V0UM00...
  • Page 13: Chapter 1 Introduction

    4131. Note: Updates to this User Manual, additional documentation and/or utilities for startWARE-GHS-V 4131, if available, may be downloaded from the NEC WEB page(s) http://www.nec.de/support 1.3 Related Documents 4131 Preliminary User’s Manual Hardware, NEC Doc. Number U15350EJ2V0UM00 4131 Preliminary Data Sheet, NEC Doc.
  • Page 14: Used Abbreviations

    Chapter 1 Introduction 1.4 Used Abbreviations There are some abbreviations used in this document, which may require additional information to be understood correctly. • RFU - reserved for future use • NC - not connected • GND - ground • GHS - Green Hills •...
  • Page 15: Chapter 2 Board Features

    Chapter 2 Board Features Startware-GHS-V 4131 is a low-cost evaluation board for NEC’s V 4131 64-bit high-performance microprocessor. It allows evaluation of the processor’s performance as well as potential system per- formance, because the V 4131 can also be operated together with its typical system environment.
  • Page 16: Figure 2-1: Simplified Block Diagram

    Chapter 2 Board Features Figure 2-1: Simplified Block Diagram Multipoint Connector Multipoint SUB-D9 SUB-D9 Connector CN11 (CN12) (CN16) (CN17) (CN3) (CN13) FPGA switch UART0 UART1 Mictor Mictor 32-bit system bus N-wire (CN6) (CN7) (CN8) Addr./Data Connector (26) CLKSEL BIGENDIAN SDRAM 96-pin VME Flash Connector...
  • Page 17: Chapter 3 Functional Description

    2 on-chip UARTs, an Ethernet Interface realized with RTL8139C, a PCI interface, a clock syn- chronous, serial interface, Real Time Clock (RTC) timers, and DMA channels. The FGPA increases the number of general purpose I/O pins. These boards are shipped with the NEC S-Boot monitor and two other monitors pre-installed in the Flash memory.
  • Page 18: Figure 3-1: Fpga Block Diagram - I/O Circuits

    Chapter 3 Functional Description Figure 3-1: FPGA Block Diagram - I/O Circuits Address WR_N Address decode and Control Logic RD_N IOCS0_N MODE_REG Data LED_DATA DIPSWITCH FLASH FP GAI N TENREG FP GAI N TPOLREG GPIO2 GPIO3 GPIO4 GPIO5 GPIO7 EPIO MODE EPIO DATA FPIO MODE FPIO DATA...
  • Page 19: Figure 3-2: Fpga State Diagram - Power On Logic

    Chapter 3 Functional Description Figure 3-2: FPGA State Diagram – Power on Logic RESET = 1 Power off POWERSWITCH = 1 POWER := 1 BATTINT_N := 1 Ignition MPOWER = 1 Power on POWERSWITCH = 0 Power on POWERSWITCH = 1 BATTINT_N := 0 Shutdown MPOWER = 0...
  • Page 20: Memory Mapping

    Chapter 3 Functional Description 3.4 Memory Mapping The V 4131 processor regards external devices like the FPGA on the evaluation board as memory mapped I/O, which is controlled with one of the external chip select signals, IOCS0#. An access to an FPGA register is executed in the same way than a memory access.
  • Page 21: Chapter 4 Detailed Functional Description

    Chapter 4 Detailed Functional Description Usage of V 4131 GPIO Pins Several GPIO pins of the V 4131 are directly used by the FPGA and other circuitry; therefore they can- not be used as user defined I/O pins. There is a total of 7 GPIOs freely usable; 4 GPIOs can additionally be used, if the debug serial I/O of the V 4131 is not used.
  • Page 22: Jumper Settings

    Chapter 4 Detailed Functional Description 4.2 Jumper Settings Before power-on, the board should be configured through the jumpers. The jumper settings are as shown in the following tables. The default setting is marked as a shaded area in the column entitled “Function”;...
  • Page 23: Table 4-4: Jumper Positions For Pipeline Clock Setting

    Chapter 4 Detailed Functional Description The corresponding jumper positions for CN26, CN28 and CN24 look as shown in table 4-4. Table 4-4: Jumper positions for pipeline clock setting CN24 CN28 CN26 PClock 199.1 MHz 181.0 MHz 165.9 MHz 153.1 MHz 132.7 MHz 99.5 MHz Preliminary User’s Manual U16417EE1V0UM00...
  • Page 24: Endianness Setting

    Chapter 4 Detailed Functional Description 4.2.2 Endianness Setting Jumper CN25 selects the endianness as described below: Table 4-5: Jumper positions for endianness setting CN25 Endianness Little Endian Big Endian 4.2.3 Data Bus Width Setting The V 4131 can work with a 32-bit wide and with a 16-bit wide memory system. A 16-bit wide bus con- figuration reduces system performance but frees 16 data lines which can then be used as GPIOs.
  • Page 25: Mips16 Enable Setting

    Chapter 4 Detailed Functional Description 4.2.4 MIPS16 Enable Setting The V 4131 supports the MIPS16 instruction set extension as defined by MIPS. However before run- ning MIPS16 code, the MIPS16EN pin must driven high during RTCRST#. Jumper CN27 defines whether the execution of MIPS16 instructions on the V 4131 is enabled or not as described below: Table 4-7: Jumper positions for MIPS16 Enable setting CN27...
  • Page 26: Jumpers For Power Supply Control

    Chapter 4 Detailed Functional Description 4.2.6 Jumpers for Power Supply Control Some jumpers on the evaluation board are just for current measurement purposes; they disconnect parts of the power supply completely when they are not present. JP2, JP3, JP4, JP9, JP10 and JP11 belong to this category.
  • Page 27: Jumpers For Debug Siu And Gpios

    Chapter 4 Detailed Functional Description Table 4-9: Jumper positions for power supply control (2/2) JP11 VDD1.5 VDD1.5 not supplied VDD1.5 supplied 4.2.7 Jumpers for Debug SIU and GPIOs The pins for the debug serial interface of the VR4131 are shared with general purpose I/O pins and can be configured to either usage with the jumpers at CN29.
  • Page 28: Figure 4-1: Jumper Positions

    Chapter 4 Detailed Functional Description Figure 4-1: Jumper positions Preliminary User’s Manual U16417EE1V0UM00...
  • Page 29: Switch Settings

    Chapter 4 Detailed Functional Description 4.3 Switch Settings 4.3.1 DIP Switch Settings The V 4131 Evaluation Board has two 8-bit DIP-switches to define several settings. Figure 4-2: DIP switch setting for SW1 and SW2 SW1 is defined as follows: Table 4-11: DIP switch setting for SW1 SW1-1 SW1-2 Boot Monitor...
  • Page 30: Other Switch Settings

    Chapter 4 Detailed Functional Description 4.3.2 Other Switch Settings The board is equipped with 4 more switches related to powering up the board. The main power switch is SW3 on the front side of the board. It directly connects power to the switching regulators and activates LEDs D1, D2 and D7.
  • Page 31: Usage Of The N-Wire Ice Connector (Cn1)

    Chapter 4 Detailed Functional Description 4.4.2 Usage of the N-Wire ICE Connector (CN1) For using the N-Wire ICE (RTE-1000-TP) connect the ICE to CN1. Figure 4-4: N-Wire Connector top view CN1 is directly connected to the V 4131 N-Wire-Interface. RMODE_N/JTDI JTCK JTMS JTDO...
  • Page 32: Using The Serial Interface (Cn16)

    Chapter 4 Detailed Functional Description 4.4.3 Using the Serial Interface (CN16) The V 4131 has two on-chip serial interfaces, called the SIU (serial interface unit) and the DSIU (debug SIU). The SIU interface conforms to the RS232-C communication standard and supports up to 1.15Mbps.
  • Page 33: Usage Of Debug Serial Interface (Cn17)

    Chapter 4 Detailed Functional Description 4.4.4 Usage of Debug Serial Interface (CN17) The pins for the debug serial interface of the V 4131 are shared with GPIOs and are software config- urable to either function. Both types of usage are supported by the V 4131 evaluation board;...
  • Page 34: Using The Fir Interface

    Chapter 4 Detailed Functional Description 4.4.5 Using the FIR Interface For using the FIR interface the N-Wire ICE (RTE-1000-TP-EE) must be disconnected from CN1. JP1 must disable the N-Wire-Interface of the V 4131. JP5 connects the IRDOUT_N/JTDO signal to the FIR module.
  • Page 35: General Purpose Ios At Cn11

    Chapter 4 Detailed Functional Description 4.4.7 General Purpose IOs at CN11 There are several possibilities to connect user hardware to the board; one of them is using I/O ports. The V 4131 evaluation board provides two kinds of I/O ports: GPIO’s are realized in the CPU (V 4131) and controlled using the respective GIU control registers in the V 4131.
  • Page 36: General Purpose Io's At Cn12 And Cn13

    Chapter 4 Detailed Functional Description 4.4.8 General Purpose IO’s at CN12 and CN13 These FPGA_I_O’s are realized in and connected to the FPGA. The CPU controls these I/O’s and each I/O can be defined as input or output separately. Control is done via a set of four registers in the FPGA: FPGA_I_O_MODEREGL, FPGA_I_O_MODEREGH, FPGA_I_O_REGL, and FPGA_I_O_REGH.
  • Page 37: Figure 4-7: Pci Connector Pin Assignment

    Chapter 4 Detailed Functional Description Figure 4-7: PCI connector pin assignment VDD3.3 SERR_N VDD3.3 AD15 CBE1 VDD5.0 VDD5.0 VDD3.3 AD14 INTA1_N VDD5.0 AD13 INTC1_N INTB1_N AD11 AD12 VDD5.0 INTD1_N AD10 VDD3.3 CBE0 VDD3.3 VDD3.3 RST_N VDD3.3 PCLK1 GNT1_N REQ1_N VDD3.3 VDD3.3 VDD3.3 AD30...
  • Page 38: I/O Board Connector Cn9

    Chapter 4 Detailed Functional Description 4.4.10 I/O Board Connector CN9 The V 4131 evaluation board offers two “specialised” extension connectors; one is referred to as I/O Board connector. It is a 160-pin (5x32) VME-style connector that carries the complete PCI bus (with REQ2_N and GNT2_N) and several additional signals like GPIOs from the CPU, FPIOs from the FPGA and power control signals of the V 4131.
  • Page 39: Ravin Board Connector Cn8

    Chapter 4 Detailed Functional Description 4.4.11 Ravin Board Connector CN8 The other “specialised” connector CN8 uses a 96-pin (3x32) VME-style connector, that carries the CPU’s buffered address and data bus and I/O control signals. Three CPU GPIOs are routed to the con- nector as well.
  • Page 40: Fpga Register Set

    Chapter 4 Detailed Functional Description 4.5 FPGA Register Set The FPGA has seventeen registers that allow to control extra I/O ports, a LED display and several other functionalities. This chapter explains the register programming functions register by register. The proc- essor should access these registers with uncached load/store operations at the addresses shown in the table below: Table 4-19: FPGA register set...
  • Page 41: Revreg (0X0A00 0000)

    FPGA_SREV (3:0) FPGA_SREV (3:0) is decoded as following: FPGA_SREV (3:0) = 0000: Rev.: y.0 others: reserved Revision of the Board (startWARE-GHS-VR4131) BOARD_REV (3:0) BOARD_REV (3:0) is decoded as following: BOARD_REV (3:0) = 0000: Rev.: 1.0 BOARD_REV (3:0) = 0001: Rev.: 2.0...
  • Page 42: Mode_Reg (0X0A00 0004)

    Chapter 4 Detailed Functional Description 4.5.2 MODE_REG (0x0A00 0004) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name Reserved Reserved Reserved POWERMODE Reserved Reserved Reserved LEDMODE Reset This register determines, how information in the LED register is used to control the 7-segment display on the board.
  • Page 43: Ledreg (0X0A00 0008)

    Chapter 4 Detailed Functional Description 4.5.3 LEDREG (0x0A00 0008) Name LED15 LED 14 LED 13 LED 12 LED 11 LED 10 LED 9 LED 8 Reset Name LED 7 LED 6 LED 5 LED 4 LED 3 LED 2 LED 1 LED 0 Reset Name...
  • Page 44 Chapter 4 Detailed Functional Description Name Function (7:0) LED (7:0) LED_1 LED_2 If LEDMODE = 0, LED (7:4) will be decoded as following: LED (7:4)= 0000: LED_1(7:0) = 1010_0000 LED (7:4)= 0001: LED_1(7:0) = 1111_1001 LED (7:4)= 0010: LED_1(7:0) = 1100_0100 LED (7:4)= 0011: LED_1(7:0) = 1101_0000 LED (7:4)= 0100:...
  • Page 45: Dipswitchreg (0X0A00 000C)

    Chapter 4 Detailed Functional Description 4.5.4 DIPSWITCHREG (0x0A00 000C) Name SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 SW1-7 SW1-8 Reset Name SW2-1 SW2-2 SW2-3 SW2-4 SW2-5 SW2-6 SW2-7 SW2-8 Reset The DIPSWITCHREG register is a read only register that reflects the setting of the switches SW1 and SW2.
  • Page 46: Flashaccreg (0X0A00 0010)

    Chapter 4 Detailed Functional Description 4.5.5 FLASHACCREG (0x0A00 0010) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name Reserved Reserved Reserved Reserved Reserved Reserved FRDY VPEN Reset This register controls write access to the on-board flash memory. If jumper JP7 is set, the V 4131 can set the VPEN pins on the on-board flash memories to active level by writing to this register.
  • Page 47: Csicontreg (0X0A00 0014)

    Chapter 4 Detailed Functional Description 4.5.6 CSICONTREG (0x0A00 0014) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name Reserved Reserved Reserved Reserved RQC1 RQC0 GNTC1 GNTC0 Reset The CSICONTREG provides a software handshake for multi-master configurations on the CSI interface of the V 4131.
  • Page 48: Fpgaintreg (0X0A00 0018)

    Chapter 4 Detailed Functional Description 4.5.7 FPGAINTREG (0x0A00 0018) Name INTA1_N INTB1_N INTC1_N INTD1_N INTA2_N INTB2_N INTC2_N INTD2_N Reset Name INTE_N FPIO4 RQC0 RQC1 Reserved Reserved Reserved LWAKE Reset This register reflects the current value of the interrupt signals of the PCI slot, the I/O Board and the on- board Ethernet controller.
  • Page 49: Fpgaintenreg (0X0A00 001C)

    Chapter 4 Detailed Functional Description 4.5.8 FPGAINTENREG (0x0A00 001C) Name INTA1_EN INTB1_EN INTC1_EN INTD1_EN INTA2_EN INTB2_EN INTC2_EN INTD2_EN Reset Name INTE_EN FPIO4_EN RQC0_EN RQC1_EN Reserved Reserved Reserved Reserved Reset This register allows to enable/disable the interrupt signals coming from the PCI slot, the I/O Board and the on-board Ethernet controller.
  • Page 50 Chapter 4 Detailed Functional Description Name Function INTA1_EN Interrupt enable for INTA1_N from PCI slot. 1: interrupt enabled Note 0: interrupt disabled Interrupt enable for INTB1_N from PCI slot. 1: interrupt enabled INTB1_EN Note 0: interrupt disabled INTC1_EN Interrupt enable for INTC1_N from PCI slot. 1: interrupt enabled Note 0: interrupt disabled...
  • Page 51: Fpgaintpolreg (0X0A00 0020)

    Chapter 4 Detailed Functional Description 4.5.9 FPGAINTPOLREG (0x0A00 0020) Name INTA1_ POL INTB1_ POL INTC1_ POL INTD1_ POL INTA2_ POL INTB2_ POL INTC2_ POL INTD2_ POL Reset Name INTE_ POL FPIO4_ POL RQC0_ POL RQC1_ POL Reserved Reserved Reserved Reserved Reset This register allows selecting the polarity of the interrupt signals coming from the PCI slot, the I/O Board and the on-board Ethernet controller.
  • Page 52 Chapter 4 Detailed Functional Description Name Function INTA1_POL Interrupt polarity of INTA1_N from PCI slot. 1: active high Note 0: active low Interrupt polarity of INTB1_N from PCI slot. 1: active high INTB1_ POL Note 0: active low INTC1_ POL Interrupt polarity of INTC1_N from PCI slot.
  • Page 53: Epio_Modereg (0X0A00 0060)

    Chapter 4 Detailed Functional Description 4.5.10 EPIO_MODEREG (0x0A00 0060) EPIOMOD EPIOMOD EPIOMOD EPIOMOD EPIOMOD EPIOMOD EPIOMOD Name Reserved (15) (13) (12) (11) (10) Reset EPIOMOD Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset This register sets the I/O mode of the EPIO(n) pins of the FPGA. The correspondence is 1 bit per pin. When the EPIOMOD bit is set to 1, the corresponding EPIO pin is set to output and the value that has been written to the corresponding EPIO bit in the EPIO_REG register is output.
  • Page 54: Epio_Reg (0X0A00 0064)

    Chapter 4 Detailed Functional Description 4.5.11 EPIO_REG (0x0A00 0064) Name EPIO (15) Reserved EPIO (13) EPIO (12) EPIO (11) EPIO (10) EPIO (9) EPIO (8) Reset Name Reserved Reserved Reserved Reserved Reserved Reserved EPIO (1) Reserved Reset This register reads and/or writes the EPIO(n) pins. The correspondence is 1 bit per pin. When 1 is set to the corresponding bit in the EPIO_MODEREG register, the data in EPIO_REG is written to the EPIO pin.
  • Page 55: Fpio_Modereg (0X0A00 0068)

    Chapter 4 Detailed Functional Description 4.5.12 FPIO_MODEREG (0x0A00 0068) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset FPIOMOD FPIOMOD FPIOMOD FPIOMOD FPIOMOD FPIOMOD Name Reserved Reserved Reset This register sets the I/O mode of the FPIO(3:0) pins. The correspondence is 1 bit per pin. When the FPIOMOD bit is set to 1, the corresponding FPIO pin is set to output and the value that has been writ- ten to the corresponding FPIO bit in the FPIO_REG register is output.
  • Page 56: Fpio_Reg (0X0A00 006C)

    Chapter 4 Detailed Functional Description 4.5.13 FPIO_REG (0x0A00 006C) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset Name Reserved Reserved FPIO (5) FPIO (4) FPIO (3) FPIO (2) FPIO (1) FPIO (0) Reset This register reads and/or writes the FPIO(5:0) pins. The correspondence is 1 bit per pin. When 1 is set to the corresponding bit in the FPIO_MODEREG register, the data in FPIO_REG is written to the corre- sponding FPIO pin.
  • Page 57: Fpga_I_O_Moderegl (0X0A00 0070)

    Chapter 4 Detailed Functional Description 4.5.14 FPGA_I_O_MODEREGL (0x0A00 0070) FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ Name MOD (15) MOD (14) MOD (13) MOD (12) MOD (11) MOD (10) MOD (9) MOD (8) Reset FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_...
  • Page 58: Fpga_I_O_Regl (0X0A00 0074)

    Chapter 4 Detailed Functional Description 4.5.15 FPGA_I_O_REGL (0x0A00 0074) FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O Name (15) (14) (13) (12) (11) (10) Reset FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O Name Reset This register reads and/or writes the FPGA_I_O (15:0) pins. The correspondence is 1 bit per pin. When 1 is set to the corresponding bit in the FPGA_I_O_MODEREGL register, the corresponding data is writ- ten to the FPGA_I_O pin.
  • Page 59: Fpga_I_O_Moderegh (0X0A00 0078)

    Chapter 4 Detailed Functional Description 4.5.16 FPGA_I_O_MODEREGH (0x0A00 0078) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ FPGA_I_O_ Name Reserved Reserved Reserved MOD (20) MOD (19) MOD (18) MOD (17) MOD (16) Reset This register sets the I/O mode of the FPGA_I_O (20:16) pins. The correspondence is 1 bit per pin. When the FPGA_I_O_MOD bit is set to 1, the corresponding FPGA_I_O pin is set to output and the value that has been written to the corresponding FPGA_I_O bit in the FPGA_I_O_REGH register is out- put.
  • Page 60: Fpga_I_O_Regh (0X0A00 007C)

    Chapter 4 Detailed Functional Description 4.5.17 FPGA_I_O_REGH (0x0A00 007C) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reset FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O FPGA_I_O Name Reserved Reserved Reserved (20) (19) (18) (17) (16) Reset This register reads and/or writes the FPGA_I_O (20:16) pins. The correspondence is 1 bit per pin. When 1 is set to the corresponding bit in the FPGA_I_O_MODEREGH register, the corresponding data is written to the FPGA_I_O pin.
  • Page 61: Chapter 5 Board Operation

    • Check if all DIP switches are in their default position • Connect the startWARE-GHS-VR4131 Evaluation board with the serial cable to a host PC with a terminal emulation program (115200 baud, 8 bit, no parity, 1 stop bit, no handshake); use the 4131 Debug Serial interface on CN17 for this purpose •...
  • Page 62: S-Boot Startup Message

    Chapter 5 Board Operation 5.2.2 S-Boot Startup Message Once the starter kit is powered up turned on, you will find this screen on the host PC. Figure 5-1: Startup Screen The screen gives information about the current system configuration, please see Figure 5-1. Remarks: 1.
  • Page 63: Flash Monitor Of Startware-Ghs-Vr4131

    Chapter 5 Board Operation 5.2.3 Flash Monitor of startWARE-GHS-VR4131 When the countdown is interrupted, the SBOOT stops boot procedure and an additional screen is shown: Figure 5-2: startWARE-GHS-V 4131 Flash Monitor Boot Menu This is the main menu of the system and provides access to various other options of the SBOOT. The user may manually boot from RAM or FLASH.
  • Page 64: Flash Options

    Chapter 5 Board Operation Start binary download and execute. Using this option starts a download of a raw binary file, recommended for larger images. Once this option is invoked, the user is asked for a) a flash memory address, where the application is downloaded to, b) a start address of the application.
  • Page 65: Figure 5-4: Startware-Ghs-Vr4131 Directory List

    Chapter 5 Board Operation Invalidate a block disables the directory entry and makes the application unavailable for the next boot process. Make block DEFAULT executable gives the option to boot an application from a block specified by the User. The application must have a valid entry in the directory block structure, before it can be started by default boot process.
  • Page 66: Reset Process Flow

    Chapter 5 Board Operation 5.2.5 Reset Process Flow Figure 5-5: startWARE-GHS-V 4131 Boot Flow Chart Reset Init Init Relocate to upper SDRAM space Default font? SDRAM Start application valid? FLASH Start application valid? Start SBOOT Preliminary User’s Manual U16417EE1V0UM00...
  • Page 67: Sboot Specification

    Chapter 5 Board Operation 5.2.6 SBOOT Specification Interrupts SBOOT does not use any interrupt. The serial units are used in polling mode only. All interrupts are routed to addresses 0x80000000, 0x80000080, 0x80000100 and 0x80000180. It is recom- mended that all user applications are making usage of the BEV bit, so that own interrupt handling routines can be entered at the desired locations.
  • Page 68: Reprogramming The Fpga

    Chapter 5 Board Operation 5.3 Reprogramming the FPGA Caution: The functions described in this chapter should only be used by experienced customers. Reprogramming the FPGA in the wrong way, may damage the board. So watch your step! A short summary how the FPGA is reprogrammed is given below. The current FPGA content has been developed with the Quartus II (Rev.
  • Page 69: Appendix A Circuit Diagrams

    Appendix A Circuit Diagrams Preliminary User’s Manual U16417EE1V0UM00...
  • Page 70 Appendix A Circuit Diagrams Preliminary User’s Manual U16417EE1V0UM00...
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  • Page 77 Appendix A Circuit Diagrams Preliminary User’s Manual U16417EE1V0UM00...
  • Page 78 [MEMO] Preliminary User’s Manual U16417EE1V0UM00...
  • Page 79: Appendix B Fpga Code

    Appendix B FPGA Code The FPGA was designed using the Quartus II design tool available through www.altera.com, version V2.0. Below the source listing of the FPGA content is shown; however changing the FPGA content should only be done by experienced board users. The source files can as well be found on the CD. B.1 File VR4131_TOP.V //************************************************ // DESIGNER...
  • Page 80 Appendix B FPGA Code input [3:0] BOARD_REV; input output X2, X3; input EPFIRCLK, POWERSWITCH, MPOWER, SPOWER; output POWER, BATTINT_N, SDRAMPOWER, SDRAMPOWER_N, SPARE; [19:0] clk_countreg_FIR; reg [5:0] clk_countreg,clk_countreg1; reg [11:0] led_test_reg; reg clk10msreg, POWER_reg, BATTINT_reg; reg [3:0] poweronseqreg; reg pwrsw; reg [3:0] pwrsw_cntr; reg pwron_rst_done;...
  • Page 81 Appendix B FPGA Code integer i; //************************************************ //Tristated ports //************************************************ PORT16 data_port (.DIN(outreg[15:0]),.DOUT(data[15:0]),.EN(!BRD_N & FPGA_READ_reg & MPOWER)); PORT1 FPGA_I_O_0 (.DIN(FPGA_I_O_reg[0]),.DOUT(FPGA_I_O[0]),.EN(FPGA_I_O_modereg[0])); PORT1 FPGA_I_O_1 (.DIN(FPGA_I_O_reg[1]),.DOUT(FPGA_I_O[1]),.EN(FPGA_I_O_modereg[1])); PORT1 FPGA_I_O_2 (.DIN(FPGA_I_O_reg[2]),.DOUT(FPGA_I_O[2]),.EN(FPGA_I_O_modereg[2])); PORT1 FPGA_I_O_3 (.DIN(FPGA_I_O_reg[3]),.DOUT(FPGA_I_O[3]),.EN(FPGA_I_O_modereg[3])); PORT1 FPGA_I_O_4 (.DIN(FPGA_I_O_reg[4]),.DOUT(FPGA_I_O[4]),.EN(FPGA_I_O_modereg[4])); PORT1 FPGA_I_O_5 (.DIN(FPGA_I_O_reg[5]),.DOUT(FPGA_I_O[5]),.EN(FPGA_I_O_modereg[5])); PORT1 FPGA_I_O_6 (.DIN(FPGA_I_O_reg[6]),.DOUT(FPGA_I_O[6]),.EN(FPGA_I_O_modereg[6])); PORT1 FPGA_I_O_7 (.DIN(FPGA_I_O_reg[7]),.DOUT(FPGA_I_O[7]),.EN(FPGA_I_O_modereg[7])); PORT1 FPGA_I_O_8 (.DIN(FPGA_I_O_reg[8]),.DOUT(FPGA_I_O[8]),.EN(FPGA_I_O_modereg[8]));...
  • Page 82 Appendix B FPGA Code //************************************************ //some initializations //************************************************ RCOSC osc (1, X1, X2, X3); assign RC_CLK = X1; assign FPGA_RESET = RESET | internal_reset; //************************************************ //Write to FPGA //************************************************ always @(posedge BWR_N or posedge FPGA_RESET) begin if (FPGA_RESET) begin BOARD_REV_0 <=(~BOARD_REV[0])&(~BOARD_REV[1])&(~BOARD_REV[2])&(~BOARD_REV[3]); MODE_REG <= 0;...
  • Page 83 Appendix B FPGA Code //************************************************ //Read register from FPGA //************************************************ always @(negedge BRD_N) begin if (MPOWER) begin case ({BIOCS0_N, address_device[24:16], address_reg[6:2]}) {1'b0, `DEV_ADDR, `DEV_OFFS+ 0}: outreg = {`FPGA_REVISION, BOARD_REV}; {1'b0, `DEV_ADDR, `DEV_OFFS+ 1}: outreg = MODE_REG; {1'b0, `DEV_ADDR, `DEV_OFFS+ 2}: outreg = led_in_reg; {1'b0, `DEV_ADDR, `DEV_OFFS+ 3}: outreg = ~DIPSWITCH;...
  • Page 84 Appendix B FPGA Code case ({BIOCS0_N, address_device[24:16]}) {1'b0, `DEV_ADDR}: FPGA_READ_reg = 1; default: FPGA_READ_reg = 0; endcase //************************************************ //LED Control //************************************************ always @(posedge clk10ms) begin if (!DIPSWITCH[8]) //Testmode begin case ({clk_countreg1[5:0]}) 6'd 0: begin led_test_reg <= led_test_reg +1; case ({led_test_reg[3:0]}) 4'b 0000: ledreg[7:0] <= `LEDPATTERN_0;...
  • Page 85 Appendix B FPGA Code case ({led_test_reg[7:4]}) 4'b 0000: ledreg[15:8] <= `LEDPATTERN_0; 4'b 0001: ledreg[15:8] <= `LEDPATTERN_1; 4'b 0010: ledreg[15:8] <= `LEDPATTERN_2; 4'b 0011: ledreg[15:8] <= `LEDPATTERN_3; 4'b 0100: ledreg[15:8] <= `LEDPATTERN_4; 4'b 0101: ledreg[15:8] <= `LEDPATTERN_5; 4'b 0110: ledreg[15:8] <= `LEDPATTERN_6; 4'b 0111: ledreg[15:8] <= `LEDPATTERN_7;...
  • Page 86 Appendix B FPGA Code case ({MODE_REG[0],led_in_reg[7:4]}) 5'b 0_0000: ledreg[15:8] <= `LEDPATTERN_0; 5'b 0_0001: ledreg[15:8] <= `LEDPATTERN_1; 5'b 0_0010: ledreg[15:8] <= `LEDPATTERN_2; 5'b 0_0011: ledreg[15:8] <= `LEDPATTERN_3; 5'b 0_0100: ledreg[15:8] <= `LEDPATTERN_4; 5'b 0_0101: ledreg[15:8] <= `LEDPATTERN_5; 5'b 0_0110: ledreg[15:8] <= `LEDPATTERN_6; 5'b 0_0111: ledreg[15:8] <= `LEDPATTERN_7;...
  • Page 87 Appendix B FPGA Code //************************************************ //Miscellaneous initialization //************************************************ assign HLDRQ_N = 1; //************************************************ //Interrupt Control //************************************************ assign INTA1_N_P = INTA1_N ~^ int_pol_reg[15]; assign INTB1_N_P = INTB1_N ~^ int_pol_reg[14]; assign INTC1_N_P = INTC1_N ~^ int_pol_reg[13]; assign INTD1_N_P = INTD1_N ~^ int_pol_reg[12]; assign IORDY_INTA2_N_P = IORDY_INTA2_N ~^ int_pol_reg[11];...
  • Page 88 Appendix B FPGA Code //************************************************ //Clock generation //************************************************ always @(posedge EPFIRCLK) begin case ({clk_countreg_FIR[19:0]}) 20'd 240000: begin clk_countreg_FIR[19:0] = 0; clk10msreg = clk10msreg ^ 1; default: clk_countreg_FIR[19:0] =clk_countreg_FIR[19:0]+1; endcase always @(posedge clk10ms) begin case ({clk_countreg1[5:0]}) 6'd 24: clk_countreg1[5:0] = 0; default: clk_countreg1[5:0] = clk_countreg1[5:0]+1;...
  • Page 89 Appendix B FPGA Code always @(posedge RC_CLK) begin if (FPGA_RESET) begin poweronseqreg <= 0; POWER_reg <= 0; BATTINT_reg <= 0; pwrsw_cntr <= 0; pwrsw <= ~POWERSWITCH; else begin if (~POWERSWITCH!= pwrsw) begin pwrsw_cntr <= pwrsw_cntr + 1; if (pwrsw_cntr == 15) pwrsw <= ~POWERSWITCH; else begin pwrsw_cntr <= 0;...
  • Page 90 Appendix B FPGA Code default: poweronseqreg <= 0; endcase assign POWER = POWER_reg; assign BATTINT_N = BATTINT_reg; assign SDRAMPOWER = (MPOWER &!MODE_REG[4]) | (SPOWER & MODE_REG[4]); assign SDRAMPOWER_N =!SDRAMPOWER; assign OSCOE = MPOWER; endmodule Preliminary User’s Manual U16417EE1V0UM00...
  • Page 91 Appendix B FPGA Code B.2 File PORT1.V //************************************************ // DESIGNER:Willi Nuesser // OBJECT :VR4131 Board // DATE :31. Oct. 2002 // REVISION:2.0 //************************************************ module PORT1(DIN, DOUT, EN); input DIN; input EN; output DOUT; reg DOUT; always@(EN or DIN) begin if(EN) DOUT=DIN;...
  • Page 92 Appendix B FPGA Code B.3 File PORT16.V //************************************************ // DESIGNER:Willi Nuesser // OBJECT :VR4131 Board // DATE :31. Oct. 2002 // REVISION:2.0 //************************************************ module PORT16(DIN, DOUT, EN); input [15:0]DIN; input EN; output [15:0]DOUT; reg [15:0]DOUT; always@(EN or DIN) begin if(EN) DOUT=DIN;...
  • Page 93 Appendix B FPGA Code B.4 File RCOSC.V //************************************************ // DESIGNER :Michael Kraemer // OBJECT :RC Oscillator // DATE :26. July 2002 // REVISION :2.0 //************************************************ module rcosc(ena, x1, x2, x3); input ena, x1; output x2, x3; wire q; assign x2 = ena? q: 0; assign x3 = x1;...
  • Page 94 Appendix B FPGA Code B.5 File VR4131.DEF //************************************************ // DESIGNER:Willi Nuesser // OBJECT :VR4131 Board // DATE :31. Oct. 2002 // REVISION:2.0 //************************************************ `define LEDPATTERN_0 8'b 1010_0000 `define LEDPATTERN_1 8'b 1111_1001 `define LEDPATTERN_2 8'b 1100_0100 `define LEDPATTERN_3 8'b 1101_0000 `define LEDPATTERN_4 8'b 1001_1001 `define LEDPATTERN_5 8'b 1001_0010 `define LEDPATTERN_6 8'b 1000_0010 `define LEDPATTERN_7 8'b 1111_1000...
  • Page 95 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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