NEC V850/SA1 mPD70F3017 Manuals

Manuals and User Guides for NEC V850/SA1 mPD70F3017. We have 1 NEC V850/SA1 mPD70F3017 manual available for free PDF download: Preliminary User's Manual

NEC V850/SA1 mPD70F3017 Preliminary User's Manual (387 pages)

32-/16-Bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 1.74 MB

- 9
  Table of Contents
21
Chapter 1 Introduction
- 21
  General
- 21
  Features
- 23
  Application Fields
- 23
  Ordering Information
- 24
  Pin Configuration (Top View)
- 27
  Function Blocks
  - 27
    Internal Block Diagram
  - 28
    On-Chip Units
31
Chapter 2 Pin Functions
- 31
  List of Pin Functions
- 37
  Pin States
- 38
  Description of Pin Functions
- 49
  Pins' I/O Circuit Types and Handling When Not Used
- 51
  Pins' I/O Circuits
53
Chapter 3 Cpu Functions
- 53
  Features
- 54
  CPU Register Set
  - 55
    Program Register Set
  - 56
    System Register Set
- 58
  Operation Modes
- 59
  Address Space
  - 59
    CPU Address Space
  - 60
    Image (Virtual Address Space)
  - 61
    Wrap-Around of CPU Address Space
  - 62
    Memory Map
  - 63
    Area
- 64
  Interrupt/Exception Table
- 67
  External Memory Area (When Expanded to 64 K, 256 K, or 1 Mbytes)
- 68
  External Memory Area (When Expanded to 4 Mbytes)
  - 69
    External Expansion Mode
- 70
  Memory Expansion Mode Register (MM) Format
- 71
  Memory Address Output Mode Register (MAM) Format
  - 72
    Recommended Use of Address Space
- 74
  Recommended Memory Map (Flash Memory Internal Version)
  - 75
    Peripheral I/O Registers
  - 80
    Specific Registers
83
Chapter 4 Bus Control Function
- 83
  Features
- 83
  Bus Control Pins and Control Register
  - 83
    Bus Control Pins
  - 84
    Control Register
- 84
  Bus Access
  - 84
    Number of Access Clocks
  - 85
    Bus Width
- 86
  Memory Block Function
- 87
  Wait Function
- 89
  Idle State Insertion Function
- 90
  Bus Hold Function
  - 90
    Outline of Function
  - 91
    Bus Hold Procedure
  - 91
    Operation in Power Save Mode
- 92
  Bus Timing
- 99
  Bus Priority
- 99
  Memory Boundary Operation Condition
  - 99
    Program Space
  - 99
    Data Space
101
Chapter 5 Interrupt/Exception Processing Function
- 101
  Features
- 102
  Interrupt Source List
  - 104
    Non-Maskable Interrupt
    - 105
      Accepting Operation
- 106
  Accepting Non-Maskable Interrupt Request
  - 107
    Restore
  - 108
    NP Flag
  - 108
    Noise Elimination Circuit of NMI Pin
  - 109
    Edge Detection Function of NMI Pin
  - 110
    Maskable Interrupts
    - 110
      Operation
- 111
  Maskable Interrupt Processing
  - 112
    Restore
  - 113
    Priorities of Maskable Interrupts
- 114
  Example of Interrupt Nesting Process
- 116
  Example of Processing Interrupt Requests Simultaneously Generated
  - 117
    Interrupt Control Register (Xxicn)
  - 119
    In-Service Priority Register (ISPR)
  - 119
    Maskable Interrupt Status Flag
  - 120
    Watchdog Timer Mode Register (WDTM)
  - 120
    Noise Elimination
  - 121
    Edge Detection Function
  - 122
    Software Exception
    - 122
      Operation
    - 123
      Restore
    - 124
      EP Flag
  - 124
    Exception Trap
    - 124
      Illegal Op Code Definition
    - 124
      Operation
    - 125
      Restore
- 126
  RETI Instruction Processing
  - 127
    Priority Control
    - 127
      Priorities of Interrupts and Exceptions
    - 127
      Multiple Interrupt Processing
  - 130
    Interrupt Latency Time
  - 130
    Periods Where Interrupt Is Not Acknowledged
131
Chapter 6 Clock Generation Function
- 131
  General
- 131
  Composition
- 132
  Clock Output Function
  - 132
    Control Registers
- 134
  Format of Power Saving Control Register (PSC)
  - 135
    Power Saving Functions
    - 135
      General
    - 136
      HALT Mode
- 137
  Operating Statuses During HALT Mode
  - 139
    IDLE Mode
  - 141
    Software STOP Mode
  - 142
    Oscillation Stabilization Time
145
Chapter 7 Timer/Counter Function
- 145
  16-Bit Timer (TM0, TM1)
  - 145
    Overview
  - 145
    Function
- 146
  Block Diagram of TM0 and TM1
  - 147
    Configuration
- 148
  Valid Edge of Tin0 Pin and Capture Trigger of Crn0
  - 150
    Timer 0, 1 Control Register
- 151
  Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1)
- 153
  Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)
- 155
  Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)
- 156
  Format of Prescaler Mode Register 0 (PRM0)
- 157
  Format of Prescaler Mode Register 1 (PRM1)
  - 158
    Operation
- 163
  Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter
- 164
  Crn1 Capture Operation with Rising Edge Specified
- 167
  Control Register Settings for Pulse Width Measurement By Restarting
  - 168
    Operation As External Event Counter
  - 169
    Operation to Output Square Wave
- 170
  Control Register Settings in Square Wave Output Mode
  - 171
    Operation to Output One-Shot Pulse
- 172
  Control Register Settings for One-Shot Pulse Output with Software Trigger
- 173
  Timing of One-Shot Pulse Output Operation with Software Trigger
- 174
  Control Register Settings for One-Shot Pulse Output with External Trigger
  - 175
    Cautions
- 176
  Timing After Changing Compare Register During Timer Count Operation
  - 177
    Operation Timing of Ovfn Flag
  - 178
    8-Bit Timer (TM2-TM5)
    - 178
      Functions
    - 179
      Configuration
    - 181
      Timer N Control Register
- 182
  Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)
- 183
  Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5)
  - 185
    Operation
- 190
  Timing of PWM Output
- 191
  Timing of Operation Based On Crn0 Transitions
- 193
  Cascade Connection Mode with 16-Bit Resolution
  - 194
    Cautions
195
Chapter 8 Watch Timer
- 195
  Function
- 196
  Configuration
- 197
  Watch Timer Control Register
- 198
  Operation
  - 198
    Operation As Watch Timer
  - 199
    Operation As Interval Timer
201
Chapter 9 Watchdog Timer
- 201
  Functions
- 202
  Runaway Detection Time for Watchdog Timer
  - 203
    Configuration
  - 203
    Watchdog Timer Control Register
- 204
  Format of Watchdog Timer Clock Selection Register (WDCS)
- 205
  Format of Watchdog Timer Mode Register (WDTM)
  - 206
    Operation
    - 206
      Operating As Watchdog Timer
    - 207
      Operating As Interval Timer
  - 208
    Standby Function Control Register
209
Chapter 10 Serial Interface Function
- 209
  Overview
- 209
  3-Wire Serial I/O (CSI0-CSI2)
  - 210
    Configuration
  - 211
    Csin Control Registers
- 212
  Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)
  - 213
    Operations
- 214
  Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)
- 215
  Timing of 3-Wire Serial I/O Mode
  - 217
    I C Bus ( Μ Μ Μ Μ PD703015Y, 70F3017Y)
    - 220
      Configuration
    - 222
      I C Control Register
- 223
  Format of IIC Control Register (IICC0)
- 227
  Format of IIC Status Register (IICS0)
- 230
  Format of IIC Clock Select Register (IICCL0)
  - 232
    I C Bus Mode Functions
- 232
  Pin Configuration Diagram
  - 233
    I C Bus Definitions and Control Methods
- 233
  Start Conditions
- 234
  Address
- 235
  Transfer Direction Specification
- 236
  ACK Signal
- 237
  Stop Condition
- 238
  Wait Signal
  - 240
    I C Interrupt Requests (INTIIC0)
  - 260
    Interrupt Request (INTIIC0) Generation Timing and Wait Control
  - 261
    Address Match Detection Method
  - 262
    Error Detection
  - 262
    Extension Code
  - 263
    Arbitration
- 264
  Arbitration Timing Example
  - 265
    Wake Up Function
  - 266
    Communication Reservation
- 267
  Communication Reservation Timing
- 268
  Timing for Accepting Communication Reservations
  - 269
    Communication Reservation Flow Chart
  - 270
    Other Cautions
  - 271
    Communication Operations
- 272
  Slave Operation Flow Chart
  - 273
    Timing of Data Communication
  - 280
    Asynchronous Serial Interface (UART0, UART1)
    - 280
      Configuration
- 281
  Block Diagram of Uartn
  - 282
    Uartn Control Registers
- 283
  Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1)
- 284
  Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)
- 285
  Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)
- 286
  Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)
  - 287
    Operations
  - 288
    Asynchronous Serial Interface (Uartn) Mode
- 293
  Relation Between Main Clock and Baud Rate
- 294
  Error Tolerance (When K = 0), Including Sampling Errors
- 295
  Format of Transmit/Receive Data in Asynchronous Serial Interface
- 297
  Timing of Asynchronous Serial Interface Transmit Completion Interrupt
- 298
  Timing of Asynchronous Serial Interface Receive Completion Interrupt
- 299
  Receive Error Timing
  - 300
    Standby Function
301
Chapter 11 A/D Converter
- 301
  Function
- 302
  Block Diagram of A/D Converter
  - 303
    Configuration
  - 305
    Control Registers
- 307
  Format of Analog Input Channel Specification Register (ADS)
  - 308
    Operation
    - 308
      Basic Operation
    - 309
      Basic Operation of A/D Converter
    - 310
      Input Voltage and Conversion Result
    - 311
      A/D Converter Operation Mode
- 312
  A/D Conversion By Hardware Start (With Falling Edge Specified)
- 313
  A/D Conversion By Software Start
  - 314
    Notes On Using A/D Converter
- 315
  Processing of Analog Input Pin
- 316
  A/D Conversion End Interrupt Generation Timing
317
Chapter 12 Dma Functions
- 317
  Functions
- 317
  Transfer Completion Interrupt Request
- 317
  Control Registers
- 318
  Format of DMA On-Chip RAM Address Registers 0 to 2 (DRA0 to DRA2)
- 319
  Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2)
321
Chapter 13 Real-Time Output Function (Rto)
- 321
  Function
- 322
  Configuration
- 323
  RTO Control Registers
- 324
  Format of Real-Time Output Port Mode Register (RTPM)
- 325
  Format of Real-Time Output Port Control Register (RTPC)
  - 326
    Operation
  - 327
    Usage
  - 327
    Notes
329
Chapter 14 Port Function
- 329
  Port Configuration
- 329
  Port Pin Function
  - 329
    Port 0
- 331
  Format of Port 0 Mode Register (PM0)
- 332
  Format of Rising Edge Enable Register (EGP0)
  - 333
    Port 1
- 334
  Format of Port 1 Mode Register (PM1)
- 335
  Format of Pull-Up Resistance Option Register 1 (PU1)
  - 336
    Port 2
- 337
  Format of Port 2 Mode Register (PM2)
- 338
  Format of Pull-Up Resistance Option Register 2 (PU2)
  - 339
    Port 3
- 340
  Format of Port 3 Mode Register (PM3)
  - 341
    Ports 4 and 5
  - 343
    Port 6
- 344
  Format of Port 6 Mode Register (PM6)
  - 345
    Ports 7 and 8
  - 346
    Port 9
- 347
  Format of Port 9 Mode Register (PM9)
  - 348
    Port 10
- 349
  Format of Port 10 Mode Register (PM10)
  - 350
    Port 11
- 351
  Format of Port 11 (P11)
- 352
  Format of Port 11 Mode Register (PM11)
  - 353
    Port 12
- 354
  Format of Port 12 Mode Register (PM12)
- 355
  Format of Port 12 Mode Control Register (PMC12)
357
Chapter 15 Reset Function
- 357
  General
- 357
  Pin Operations
359
CHAPTER 16 FLASH MEMORY ( Μ Μ Μ Μ PD70F3017, 70F3017Y)
- 359
  Features
- 359
  Writing By Flash Writer
- 360
  Programming Environment
- 360
  Communication System
- 362
  Pin Connection
  - 362
    VPP Pin
  - 362
    Serial Interface Pin
  - 364
    RESET Pin
  - 364
    Port Pin
  - 364
    Other Signal Pins
  - 364
    Power Supply
- 365
  Programming Method
  - 365
    Flash Memory Control
  - 365
    Flash Memory Programming Mode
  - 366
    Selection of Communication Mode
  - 366
    Communication Command
  - 367
    Resources Used
369
Appendix Aregister Index
375
Appendix Blist of Instrution Set
383
Appendix Cindex

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NEC V850/SA1 mPD70F3017 Manuals

Manuals and User Guides for NEC V850/SA1 mPD70F3017. We have 1 NEC V850/SA1 mPD70F3017 manual available for free PDF download: Preliminary User's Manual

NEC V850/SA1 mPD70F3017 Preliminary User's Manual (387 pages)

Table of Contents

21 Chapter 1 Introduction

31 Chapter 2 Pin Functions

53 Chapter 3 Cpu Functions

83 Chapter 4 Bus Control Function

101 Chapter 5 Interrupt/Exception Processing Function

131 Chapter 6 Clock Generation Function

145 Chapter 7 Timer/Counter Function

195 Chapter 8 Watch Timer

201 Chapter 9 Watchdog Timer

209 Chapter 10 Serial Interface Function

301 Chapter 11 A/D Converter

317 Chapter 12 Dma Functions

321 Chapter 13 Real-Time Output Function (Rto)

329 Chapter 14 Port Function

357 Chapter 15 Reset Function

359 CHAPTER 16 FLASH MEMORY ( Μ Μ Μ Μ PD70F3017, 70F3017Y)

369 Appendix Aregister Index

375 Appendix Blist of Instrution Set

383 Appendix Cindex

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21
Chapter 1 Introduction

31
Chapter 2 Pin Functions

53
Chapter 3 Cpu Functions

83
Chapter 4 Bus Control Function

101
Chapter 5 Interrupt/Exception Processing Function

131
Chapter 6 Clock Generation Function

145
Chapter 7 Timer/Counter Function

195
Chapter 8 Watch Timer

201
Chapter 9 Watchdog Timer

209
Chapter 10 Serial Interface Function

301
Chapter 11 A/D Converter

317
Chapter 12 Dma Functions

321
Chapter 13 Real-Time Output Function (Rto)

329
Chapter 14 Port Function

357
Chapter 15 Reset Function

359
CHAPTER 16 FLASH MEMORY ( Μ Μ Μ Μ PD70F3017, 70F3017Y)

369
Appendix Aregister Index

375
Appendix Blist of Instrution Set

383
Appendix Cindex