Page 1 User’s Manual PD78058F, 78058FY Subseries 8-Bit Single-Chip Microcontrollers PD78056F PD78058F PD78P058F PD78058F(A) PD78056FY PD78058FY PD78P058FY PD78058FY(A) Document No. U12068EJ2V0UM00 (2nd edition) Date Published April 1998 N CP (K) © 1997 Printed in Japan...
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Page 3 Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, and IEBus are trademarks of NEC Corporation. MS-DOS, Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corpo- ration in the United States and/or other countries.
Page 4 The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 MAJOR REVISIONS IN THIS EDITION Page Throughout The following products have already been developed: PD78056FGC- -8BT, 78058FGC- 78058FYGC- -8BT P133 to The block diagrams of the following ports were changed. P137, P143 Figures 6-5 and 6-7 P20, P21, P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block Diagram, Figure 6-9 P30 to P37 Block Diagram, Figure 6-16 P71 and P72 Block Diagram P159 Table 7-2 Relationship between CPU Clock and Minimum Instruction Execution Time was added.
Page 7 (common to the 78K/0 Series). PD78058F, 78058FY Pin functions Internal block functions Interrupt Other on-chip peripheral functions PREFACE PD78056F, 78058F, 78P058F, 78058F(A) PD78056FY, 78058FY, 78P058FY, 78058FY(A) Subseries User’s Manual (This Manual) CPU functions Instruction set...
Page 8 How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. For persons who use this manual as the manual for the 78058FY(A), The PD78058F and 78058FY differ from the PD78058F(A) and 78058FY(A) only in their quality grades.
Page 9 Chapter Organization This manual divides the descriptions for the PD78058F and 78058FY Subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9...
Page 10 Differences between PD78058F and PD78058FY Subseries: The PD78058F and PD78058FY Subseries are different in the following functions of the serial interface channel 0. Modes of Serial Interface Channel 0 3-wire serial I/O mode 2-wire serial I/O mode SBI (serial bus interface) mode C bus mode : Supported —...
Page 11 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related Documents for PD78058F Subseries Document Name PD78056F, 78058F Data Sheet PD78P058F Data Sheet PD78058F(A) Data Sheet PD78058F, 78058FY Subseries User’s Manual 78K/0 Series User’s Manual—Instruction...
Page 12 Development Tool Documents (User’s Manuals) Document Name RA78K0 Assembler Package RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler CC78K0 C Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS™) Base PG-1500 Controller IBM PC Series (PC DOS™) Base IE-78K0-NS IE-78001-R-A IE-780308-NS-EM1...
Page 13 IC PACKAGE MANUAL Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices Reliability Quality Control on NEC Semiconductor Devices Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Quality Assurance for Semiconductor Devices Microcontroller Related Product Guide — Third Party Manufacturers Caution The above documents are subject to change without prior notice.
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Page 15: Table Of Contents
CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) ... 35 1.1 Features ... 35 1.2 Applications ... 36 1.3 Ordering Information ... 36 1.4 Quality Grade ... 37 1.5 Pin Configuration (Top View) ... 38 1.6 78K/0 Series Expansion ... 41 1.7 Block Diagram ... 43 1.8 Outline of Function ...
Page 16 3.2.14 AV 3.2.15 RESET ... 3.2.16 X1 and X2 ... 3.2.17 XT1 and XT2 ... 3.2.18 V 3.2.19 V 3.2.20 V (PROM versions only) ... 3.2.21 IC (Mask ROM version only) ... 3.3 Input/output Circuits and Recommended Connection of Unused Pins ... 73 CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) ...
Page 17 5.2.1 Control registers ... 103 5.2.2 General registers ... 106 5.2.3 Special Function Register (SFR) ... 108 5.3 Instruction Address Addressing ... 112 5.3.1 Relative addressing ... 112 5.3.2 Immediate addressing ... 113 5.3.3 Table indirect addressing ... 114 5.3.4 Register addressing ...
Page 18 7.4.2 Subsystem clock oscillator ... 162 7.4.3 Scaler ... 164 7.4.4 When no subsystem clocks are used ... 164 7.5 Clock Generator Operations ... 165 7.5.1 Main system clock operations ... 166 7.5.2 Subsystem clock operations ... 167 7.6 Changing System Clock and CPU Clock Settings ... 167 7.6.1 Time required for switchover between system clock and CPU clock ...
Page 19 CHAPTER 11 WATCHDOG TIMER ... 245 11.1 Watchdog Timer Functions ... 245 11.2 Watchdog Timer Configuration ... 247 11.3 Watchdog Timer Control Registers ... 248 11.4 Watchdog Timer Operations ... 251 11.4.1 Watchdog timer operation ... 251 11.4.2 Interval timer operation ... 252 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT ...
Page 20 16.4.3 SBI mode operation ... 305 16.4.4 2-wire serial I/O mode operation ... 331 16.4.5 SCK0/P27 pin output manipulation ... 336 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) ... 337 17.1 Serial Interface Channel 0 Functions ... 338 17.2 Serial Interface Channel 0 Configuration ...
Page 21 21.2 Interrupt Sources and Configuration ... 478 21.3 Interrupt Function Control Registers ... 482 21.4 Interrupt Servicing Operations ... 491 21.4.1 Non-maskable interrupt acknowledge operation ... 491 21.4.2 Maskable Interrupt request reception ... 494 21.4.3 Software interrupt request acknowledge operation ... 497 21.4.4 Multiple interrupt servicing ...
Page 22 26.3.3 PROM read procedure ... 546 26.4 Screening of One-Time PROM Versions ... 547 CHAPTER 27 INSTRUCTION SET ... 549 27.1 Legends Used in Operation List ... 550 27.1.1 Operand identifiers and description methods ... 550 27.1.2 Description of “operation” column ... 551 27.1.3 Description of “flag”...
Page 23 Memory Map ( PD78056F, 78056FY) ... Memory Map ( PD78058F, 78058FY) ... Memory Map ( PD78P058F, PD78P058FY) ... Data Memory Addressing ( PD78056F, 78056FY) ... Data Memory Addressing ( PD78058F, 78058FY) ... Data Memory Addressing ( PD78P058F, 78P058FY) ... Program Counter Format ...
Page 24 Figure No. Oscillation Mode Selection Register Format ... Main System Clock Waveform due to Writing to OSMS ... External Circuit of Main System Clock Oscillator ... External Circuit of Subsystem Clock Oscillator ... Examples of Resonator with Incorrect Connection ... Main System Clock Stop Function ...
Page 25 Figure No. 8-31 Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger ... 8-32 Timing of One-Shot Pulse Output Operation Using Software Trigger ... 8-33 Control Register Settings for One-Shot Pulse Output Operation Using External Trigger ... 8-34 Timing of One-Shot Pulse Output Operation Using External Trigger (with Rising Edge Specified) ..
Page 26 Figure No. 14-1 A/D Converter Block Diagram ... 14-2 A/D Converter Mode Register Format ... 14-3 A/D Converter Input Select Register Format ... 14-4 External Interrupt Mode Register 1 Format ... 14-5 A/D Converter Basic Operation ... 14-6 Relationship Between Analog Input Voltage and A/D Conversion Result ... 14-7 A/D Conversion by Hardware Start ...
Page 27 Figure No. 16-27 Address Transmission from Master Device to Slave Device (WUP = 1) ... 16-28 Command Transmission from Master Device to Slave Device ... 16-29 Data Transmission from Master Device to Slave Device ... 16-30 Data Transmission from Slave Device to Master Device ... 16-31 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ...
Page 28 Figure No. 18-5 Automatic Data Transmit/Receive Interval Specify Register Format ... 18-6 3-Wire Serial I/O Mode Timings ... 18-7 Circuit of Switching in Transfer Bit Order ... 18-8 Basic Transmission/Reception Mode Operation Timings ... 18-9 Basic Transmission/Reception Mode Flowchart ... 18-10 Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) ...
Page 29 Figure No. 20-4 Real-time Output Port Mode Register Format ... 20-5 Real-time Output Port Control Register Format ... 21-1 Basic Configuration of Interrupt Function ... 21-2 Interrupt Request Flag Register Format ... 21-3 Interrupt Mask Flag Register Format ... 21-4 Priority Specify Flag Register Format ...
Page 30 Figure No. 25-1 Block Diagram of ROM Correction ... 25-2 Correction Address Registers 0 and 1 Format ... 25-3 Correction Control Register Format ... 25-4 Storing Example to EEPROM (When One Place Is Corrected) ... 25-5 Connecting Example with EEPROM (Using 2-Wire Serial I/O Mode) ... 25-6 Initialization Routine ...
Page 31 Table No. Differences Between the PD78058F and PD78058F(A) ... Mask Options of Mask POM Versions ... Differences Between the PD78058FY and PD78058FY(A) ... Mask Options of Mask ROM Versions ... Pin Input/Output Circuit Types ... Pin Input/Output Circuit Types ... Vector Table ...
Page 32 Table No. 9-10 Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter ... 10-1 Interval Timer Interval Time ... 10-2 Watch Timer Configuration ... 10-3 Interval Timer Interval Time ... 11-1 Watchdog Timer Runaway Detection Times ... 11-2 Interval Times ...
Page 33 Table No. 20-2 Operation in Real-time Output Buffer Register Manipulation ... 20-3 Real-time Output Port Operating Mode and Output Trigger ... 21-1 Interrupt Source List ... 21-2 Various Flags Corresponding to Interrupt Request Sources ... 21-3 Times from Maskable Interrupt Request Generation to Interrupt Service ... 21-4 Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing ...
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Page 35: Chapter 1 Outline ( Pd78058F Subseries)
1.1 Features Compared to the conventional reduced. On-chip high-capacity ROM and RAM Item Program Memory (ROM) Part Number PD78056F 48 Kbytes PD78058F 60 Kbytes Note 1 PD78P058F 60 Kbytes Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS).
Page 36: Applications
CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) 1.2 Applications In the case of the PD78056F, 78058F and 78P058F, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPC’s, fuzzy home appliances, vending machines, etc. In the case of the PD78058F (A), Controllers for car electronics, gas detection and shut-off devices, various safety devices, etc.
Page 37: Quality Grade
ROM code suffix. Please refer to Quality grade on NEC Semiconductor Devices (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Package 14 mm, Resin thickness: 2.7 mm) 14 mm, Resin thickness: 1.4 mm)
Page 38: Pin Configuration (Top View)
CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) 1.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm) PD78056FGC- -3B9, 78058FGC- 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) PD78056FGC- -8BT, 78058FGC- 80-pin plastic TQFP (Fine pitch) (12 PD78058FGK- -BE9...
Page 39 CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) Pin Identifications A8 to A15 Address Bus AD0 to AD7 Address/Data Bus ANI0 to ANI7 Analog Input ANO0, ANO1 Analog Output ASCK Asynchronous Serial Clock ASTB Address Strobe Analog Power Supply Analog Reference Voltage REF0, 1 Analog Ground BUSY...
Page 40 CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) (2) PROM programming mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm) PD78P058FGC-3B9 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) PD78P058FGC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Cautions 1.
Page 41: Series Expansion
CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) 1.6 78K/0 Series Expansion The 78K/0 Series expansion is shown below. The names in frames are subseries. Control 100-pin PD78075B PD78078 PD78078Y 100-pin PD78070A PD78070AY 100-pin PD780018AY 100-pin PD780058 PD780058Y 80-pin PD78058F PD78058FY 80-pin 80-pin PD78054 PD78054Y...
Page 42 CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) The differences between the major functions of each subseries are shown below. Function Capacity Subseries 8-bit 16-bit Watch WDT Control PD78075B 32 K to 40 K 4 ch PD78078 48 K to 60 K PD78070A —...
Page 43: Block Diagram
CHAPTER 1 OUTLINE ( PD78058F SUBSERIES) 1.7 Block Diagram TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SERIAL...
Page 44: Outline Of Function
1. The capacities of the internal PROM and the internal high-speed RAM can be changed using the memory size switching register (IMS). 2. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size switching register (IXS). PD78056F PD78058F Mask ROM 48 Kbytes...
Page 45: Differences Between The Pd78058F And Pd78058F(A)
1.9 Differences Between the PD78058F and PD78058F(A) Table 1-1. Differences Between the PD78058F and PD78058F(A) Part Number Item Quality grade Package PD78056F PD78058F 1.2 kHz, 2.4 kHz, 4.9 KHz, 9.8 kHz (main system clock at 5.0-MHz operation) Internal: 13 External: 7...
Page 46: Mask Options
1.10 Mask Options There are mask options in the mask ROM versions ( PD78056F, 78058F). By specifying the mask option when ordering, you can have the pull-up resistors shown in Table 1-2 incorporated on-chip. If a mask option is used when pull-up resistors are required, the number of parts can be reduced and package area can be shrunk.
Page 47: Chapter 2 Outline ( Pd78058Fy Subseries)
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) 2.1 Features Compared to the conventional PD78054Y Subseries, EMI (Electro Magnetic Interference) noise has been reduced. On-chip high-capacity ROM and RAM Item Program Memory (ROM) Part Number PD78056FY 48 Kbytes PD78058FY 60 Kbytes PD78P058FY Note 1 60 Kbytes Notes...
Page 48: Applications
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) 2.2 Applications In the case of the PD78056FY, 78058FY and 78P058FY, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. In the case of the PD78058FY (A), Controllers for car electronics, gas detection and shut-off devices, various safety devices, etc.
Page 49: Quality Grade
ROM code suffix. Please refer to Quality grade on NEC Semiconductor Devices (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Package 14 mm, Resin thickness: 2.7 mm) 14 mm, Resin thickness: 1.4 mm)
Page 50: Pin Configuration (Top View)
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) 2.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm) PD78056FYGC- -3B9, 78058FYGC- 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) PD78056FYGC- -8BT, 78058FYGC- 80-pin plastic TQFP (Fine pitch) (12 PD78058FYGK- -BE9...
Page 51 CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) Pin Identifications A8 to A15 Address Bus AD0 to AD7 Address/Data Bus ANI0 to ANI7 Analog Input ANO0, ANO1 Analog Output ASCK Asynchronous Serial Clock ASTB Address Strobe Analog Power Supply Analog Reference Voltage REF0, 1 Analog Ground BUSY...
Page 52 CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) (2) PROM programming mode 80-pin plastic QFP (14 14 mm, Resin thickness: 2.7 mm) PD78P058FYGC-3B9 80-pin plastic QFP (14 14 mm, Resin thickness: 1.4 mm) Note PD78P058FYGC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note Under development Cautions 1.
Page 53: Series Expansion
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) 2.6 78K/0 Series Expansion The 78K/0 Series expansion is shown below. The names in frames are subseries. Control 100-pin PD78075B 100-pin PD78078 PD78078Y PD78070A PD78070AY 100-pin PD780018AY 100-pin PD780058 PD780058Y 80-pin 80-pin PD78058F PD78058FY 80-pin PD78054 PD78054Y...
Page 54 CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) The differences between the major functions of each subseries are shown below. Function Subseries Capacity Control PD78078Y 48 K to 60 K PD78070AY — PD780018AY 48 K to 60 K PD780058Y 24 K to 60 K PD78058FY 48 K to 60 K PD78054Y...
Page 55: Block Diagram
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) 2.7 Block Diagram TO0/P30 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SERIAL SO0/SB1/SDA1/P26 INTERFACE 0 SCK0/SCL/P27 SI1/P20 SO1/P21 SERIAL...
Page 56: Outline Of Function
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) 2.8 Outline of Function Part Number Item Internal memory High-speed RAM Buffer RAM Expansion RAM Memory space General register Minimum With main system clock selected instruction execution With subsystem clock selected time Instruction set I/O port A/D converter D/A converter...
Page 57: Differences Between The Pd78058Fy And Pd78058Fy(A)
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) Part Number Item Vectored Maskable interrupt sources Non-maskable Software Test input Supply voltage Operating ambient temperature Package Note Under development for the PD78P058FY only. 2.9 Differences Between the PD78058FY and PD78058FY(A) Table 2-1. Differences Between the PD78058FY and PD78058FY(A) Part Number Item Quality grade...
Page 58: Mask Options Of Mask Rom Versions
CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES) 2.10 Mask Options The mask ROM versions ( PD78056FY, 78058FY) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production.
Page 59: Chapter 3 Pin Function ( Pd78058F Subseries)
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Input Port 0. Input/ 8-bit input/output port. output Note 1 Input P10 to P17 Input/ Port 1. output 8-bit input/output port.
Page 60 CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Input/ Port 3. output 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software.
Page 61 CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Input/ Port 12. output 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. P130, P131 Input/ Port 13.
Page 62 CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output INTP0 Input External interrupt request inputs with specifiable valid edges (rising INTP1 edge, falling edge, both rising and falling edges). INTP2 INTP3 INTP4 INTP5 INTP6 Input Serial interface serial data input Output Serial interface serial data output...
Page 63 CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input/Output A8 to A15 Output High-order address bus when expanding external memory Strobe signal output for read operation from external memory Output Strobe signal output for write operation to external memory WAIT...
Page 64: Prom Programming Mode Pins (Prom Versions Only)
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.1.2 PROM programming mode pins (PROM versions only) Pin Name Input/Output RESET Input PROM programming mode setting. When +5 V or +12.5 V is applied to the V the PROM programming mode is set. Input High-voltage application for PROM programming mode setting and program write/verify.
Page 65: Description Of Pin Functions
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.
Page 66: P10 To P17 (Port 1)
These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output functions. (a) SI0, SI1, SO0, SO1 Serial interface serial data input/output pins (b) SCK0 and SCK1 Serial interface serial clock input/output pins (c) SB0 and SB1 NEC standard serial bus interface input/output pins...
Page 67: P30 To P37 (Port 3)
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface pin, the I/O and output latches must be set according to the function the user requires.
Page 68: P40 To P47 (Port 4)
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified in 8-bit units.
Page 69: P70 To P72 (Port 7)
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 6 (PM6). P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option. When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL).
Page 70: P120 To P127 (Port 12)
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 71: Av Dd
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.2.13 AV This is the analog power supply pin of the A/D converter and the port’s power supply pin. Always use the same voltage as that of the V pin even when the A/D converter is not used. 3.2.14 AV This is the ground potential pin for the A/D converter and D/A converter, and the ground potential pin for the port.
Page 72: Ic (Mask Rom Version Only)
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.2.21 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78058F Subseries at delivery. Connect it directly to the V with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and V is too long or an external noise is input to the IC pin, the user's program may not run normally.
Page 73: Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1.
Page 74 CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name P60 to P63 (Mask ROM version) P60 to P63 (PROM version) P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 RESET REF0 REF1 IC (Mask ROM version)
Page 75: List Of Pin Input/Output Circuit
CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) Figure 3-1. List of Pin Input/Output Circuit (1/2) Type 2 Schmitt-Triggered Input with Hysteresis Characteristics Type 5-J pull-up enable data P-ch output N-ch disable input enable Type 5-O pull-up enable data P-ch output N-ch disable Type 8-D...
Page 76 CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES) Figure 3-1. List of Pin Input/Output Circuit (2/2) Type 12-B pullup enable data P-ch output N-ch disable input P-ch enable analog output voltage N-ch Type 13-H data N-ch output disable P-ch medium breakdown input buffer Type 13-I P-ch...
Page 77: Chapter 4 Pin Function ( Pd78058Fy Subseries)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Input Port 0. Input/ 8-bit input/output port. output Note 1 Input P10 to P17 Input/ Port 1. output 8-bit input/output port.
Page 78 CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Input/ Port 3. output 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software.
Page 79 CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output P120 to P127 Input/ Port 12. output 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. P130 to P131 Input/ Port 13.
Page 80 CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) (2) Non-port pins (1/2) Pin Name Input/Output INTP0 Input External interrupt request inputs with specifiable valid edges (rising INTP1 edge, falling edge, both rising and falling edges). INTP2 INTP3 INTP4 INTP5 INTP6 Input Serial interface serial data input Output Serial interface serial data output...
Page 81 CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input/Output A8 to A15 Output High-order address bus when expanding external memory Output Strobe signal output for read operation from external memory Strobe signal output for write operation to external memory WAIT Input...
Page 82: Prom Programming Mode Pins (Prom Versions Only)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.1.2 PROM programming mode pins (PROM versions only) Pin Name Input/Output RESET Input PROM programming mode setting. When +5 V or +12.5 V is applied to the V the PROM programming mode is set. Input High-voltage application for PROM programming mode setting and program write/verify.
Page 83: Description Of Pin Functions
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.
Page 84: P10 To P17 (Port 1)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 85: P30 To P37 (Port 3)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output, and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 86: P40 To P47 (Port 4)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified in 8-bit units.
Page 87: P70 To P72 (Port 7)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise.
Page 88: P120 To P127 (Port 12)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports.
Page 89: Av Dd
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2.13 AV This is the analog power supply pin of the A/D converter and the port’s power supply pin. Always use the same voltage as that of the V pin even when the A/D converter is not used. 4.2.14 AV This is the ground potential pin for the A/D converter and D/A converter, and the ground potential pin for the port.
Page 90: Ic (Mask Rom Version Only)
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.2.21 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD78058FY Subseries at delivery. Connect it directly to the V with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and V is too long or an external noise is input to the IC pin, the user's program may not run normally.
Page 91: Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) 4.3 Input/output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended connection for unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1.
Page 92 CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name P60 to P63 (Mask ROM version) P60 to P63 (PROM version) P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 to P127/RTP7 P130/ANO0 to P131/ANO1 RESET REF0 REF1...
Page 93: List Of Pin Input/Output Circuit
CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) Figure 4-1. List of Pin Input/Output Circuit (1/2) Type 2 Schmitt-Triggered Input with Hysteresis Characteristics Type 5-J pullup enable data P-ch output N-ch disable input enable Type 5-O pullup enable data P-ch output N-ch disable Type 8-D...
Page 94 CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES) Figure 4-1. List of Pin Input/Output Circuit (2/2) Type 12-B pullup enable data P-ch output N-ch disable input P-ch enable analog output voltage N-ch Type 13-H data N-ch output disable P-ch medium breakdown input buffer Type 13-I P-ch...
Page 95: Chapter 5 Cpu Architecture
5.1 Memory Spaces 64-Kbyte memory spaces can be accessed in the PD78058F, 78058FY Subseries. Figures 5-1 to 5-3 show memory maps. Figure 5-1. Memory Map ( PD78056F, 78056FY) FFFFH FF00H FEFFH FEE0H FEDFH FB00H FAFFH FAE0H FADFH FAC0H Data memory...
Page 96: Memory Map ( Pd78058F, 78058Fy)
Figure 5-2. Memory Map ( PD78058F, 78058FY) FFFFH FF00H FEFFH FEE0H FEDFH FB00H FAFFH FAE0H FADFH FAC0H Data memory FABFH space F800H F7FFH F400H F3FFH F000H EFFFH Program memory space 0000H Note When internal ROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the memory size switching register (IMS).
Page 97: Memory Map ( Pd78P058F, Pd78P058Fy)
Figure 5-3. Memory Map ( PD78P058F, PD78P058FY) FFFFH FF00H FEFFH General Registers FEE0H FEDFH Internal High-speed RAM FB00H FAFFH FAE0H FADFH FAC0H Data memory FABFH space F800H F7FFH F400H F3FFH F000H EFFFH Program memory space 0000H Note When internal PROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal PROM size to less than 56 Kbytes by the memory size switching register (IMS).
Page 98: Internal Program Memory Space
5.1.1 Internal program memory space The PD78056F and PD78056FY are Mask ROM with a 49152 x 8 bit configuration, the PD78058F and PD78058FY are Mask ROM with a 61440 x 8 bit configuration and the PD78P058F and PD78P058FY are PROM with a 61440 x 8 bit configuration.
Page 99: Internal Data Memory Space
(2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 5.1.2 Internal data memory space The PD78058F and 78058FY Subseries units incorporate the following RAMs.
Page 100: Data Memory Addressing
(SFR), general purpose register, etc., is possible. Figure 5-4 to 5-6 show the data memory addressing modes. For details of each addressing, refer to Section 5.4 Operand Address Addressing. Figure 5-4. Data Memory Addressing ( PD78056F, 78056FY) FFFFH Special Function...
Page 101: Data Memory Addressing ( Pd78058F, 78058Fy)
Figure 5-5. Data Memory Addressing ( PD78058F, 78058FY) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM 8 bits FAC0H FABFH...
Page 102: Data Memory Addressing ( Pd78P058F, 78P058Fy)
Figure 5-6. Data Memory Addressing ( PD78P058F, 78P058FY) FFFFH Special Function Registers (SFRs) 8 bits FF20H FF1FH FF00H FEFFH General Registers 8 bits FEE0H FEDFH Internal High-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM 8 bits FAC0H FABFH...
Page 103: Processor Registers
5.2 Processor Registers The PD78058F and 78058FY Subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 104 (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except non-maskable interrupt requests are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specify flag.
Page 105: Stack Pointer Format
(3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH) can be set as the stack area. SP15 SP14 SP13 SP12 SP11 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
Page 106: General Registers
5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL).
Page 107: General Register Configuration
CHAPTER 5 CPU ARCHITECTURE Figure 5-12. General Register Configuration FEFFH BANK0 FEF8H FEF7H BANK1 FEE0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H (a) Absolute Name 16-Bit Processing (b) Function Name 16-Bit Processing 8-Bit Processing 8-Bit Processing...
Page 108: Special Function Register (Sfr)
5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.
Page 109: Special-Function Register List
Table 5-3. Special-Function Register List (1/3) Address Special-Function Register (SFR) Name FF00H Port0 FF01H Port1 FF02H Port2 FF03H Port3 FF04H Port4 FF05H Port5 FF06H Port6 FF07H Port7 FF0CH Port12 FF0DH Port13 FF10H Capture/compare register 00 FF11H Capture/compare register 01 FF12H FF13H 16-bit timer register FF14H...
Page 110 Table 5-3. Special-Function Register List (2/3) Address Special-Function Register (SFR) Name FF38H Correction address register 0 FF39H FF3AH Correction address register 1 FF3BH FF40H Timer clock select register 0 FF41H Timer clock select register 1 FF42H Timer clock select register 2 FF43H Timer clock select register 3 FF47H...
Page 111 1. The external access area cannot be accessed in SFR addressing. Access the area with direct addressing. 2. The value after reset depends on products. PD78056F, 78056FY: CCH, PD78058F, 78058FY: CFH, PD78P058F, 78P058FY: CFH 3. This register is provided only in the PD78058F, 78058FY, 78P058F, and 78P058FY. CHAPTER 5 CPU ARCHITECTURE...
Page 112: Instruction Address Addressing
5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The contents of PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing.
Page 113: Immediate Addressing
5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11 instruction branches to an area of addresses 0800H through 0FFFH.
Page 114: Table Indirect Addressing
5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire memory space.
Page 115: Register Addressing
5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] CHAPTER 5 CPU ARCHITECTURE...
Page 116: Operand Address Addressing
5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly) addressed.
Page 117: Register Addressing
5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
Page 118: Direct Addressing
5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier addr16 [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] OP code saddr16 (low) saddr16 (high) CHAPTER 5 CPU ARCHITECTURE Description...
Page 119: Short Direct Addressing
5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 120 [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code [Illustration] OP code saddr-offset Effective Address When 8-bit immediate data is 20H to FFH, When 8-bit immediate data is 00H to 1FH, CHAPTER 5 CPU ARCHITECTURE 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0...
Page 121: Special-Function Register (Sfr) Addressing
5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier Special-function register name...
Page 122: Register Indirect Addressing
5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code.
Page 123: Based Addressing
5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1).
Page 124: Based Indexed Addressing
5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1).
Page 125: Chapter 6 Port Functions
6.1 Port Functions The PD78058F and 78058FY Subseries units incorporate two input ports and sixty-seven input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/ output pins.
Page 126: Port Functions ( Pd78058F Subseries)
Table 6-1. Port Functions ( PD78058F Subseries) (1/2) Pin Name Port 0. 8-bit input/output port. P10 to P17 Port 1. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. Port 2.
Page 127 Table 6-1. Port Functions ( PD78058F Subseries) (2/2) Pin Name Port 6. 8-bit input/output port. Input/output mode can be specified bit-wise. Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. P120 to P127 Port 12.
Page 128: Port Functions ( Pd78058Fy Subseries)
Table 6-2. Port Functions ( PD78058FY Subseries) (1/2) Pin Name Port 0. 8-bit input/output port. P10 to P17 Port 1. 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. Port 2.
Page 129 Table 6-2. Port Functions ( PD78058FY Subseries) (2/2) Pin Name Port 6. 8-bit input/output port. Input/output mode can be specified bit-wise. Port 7. 3-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. P120 to P127 Port 12.
Page 130: Port Configuration
6.2 Port Configuration A port consists of the following hardware: Item Control register Port Pull-up resistor Note MM specifies I/O for port 4. 6.2.1 Port 0 Port 0 is an 8-bit input/output port with output latch. P01 to P06 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (PM0).
Page 131: P00 And P07 Block Diagram
CHAPTER 6 PORT FUNCTIONS Figure 6-2. P00 and P07 Block Diagram Figure 6-3. P01 to P06 Block Diagram PUO0 PORT Output Latch (P01 to P06) PM01 to PM06 PUO : Pull-up resistor option register PM : Port mode register : Port 0 read signal WR : Port 0 write signal P00/INTP0/TI00, P07/XT1...
Page 132: Port 1
6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 133: Port 2 ( Pd78058F Subseries)
6.2.3 Port 2 ( PD78058F Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 134: P22 And P27 Block Diagram
Figure 6-6. P22 and P27 Block Diagram PUO2 PORT Output Latch (P22, P27) PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal CHAPTER 6 PORT FUNCTIONS Selector P-ch P22/SCK1,...
Page 135: Port 2 ( Pd78058Fy Subseries)
6.2.4 Port 2 ( PD78058FY Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 136: P22 And P27 Block Diagram
Figure 6-8. P22 and P27 Block Diagram PUO2 PORT Output Latch (P22 and P27) PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal CHAPTER 6 PORT FUNCTIONS Selector P-ch...
Page 137: Port 3
6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 138: Port 4
6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on- chip pull-up resistor can be used to them in 8-bit units with pull-up resistor option register L (PUOL).
Page 139: Port 5
6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 140: Port 6
6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions depending on whether the higher 4 bits or lower 4 bits of a port are used, and whether the mask ROM model or PROM model is used.
Page 141: P60 To P63 Block Diagram
CHAPTER 6 PORT FUNCTIONS Figure 6-13. P60 to P63 Block Diagram PORT Output Latch (P60 to P63) PM60 to PM63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14. P64 to P67 Block Diagram PUO6 PORT Output Latch...
Page 142: Port 7
6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).
Page 143: P71 And P72 Block Diagram
CHAPTER 6 PORT FUNCTIONS Figure 6-16. P71 and P72 Block Diagram PUO7 PORT Output Latch (P71 and P72) PM71, PM72 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 7 read signal WR : Port 7 write signal P-ch Selector P71/SO2/TxD,...
Page 144: Port 12
6.2.10 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 12 (PM12). When pins P120 to P127 are used as input port pins, an on-chip pull-up resistor can be used as an 8-bit unit by means of pull-up resistor option register H (PUOH).
Page 145: Port 13
6.2.11 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor can be used as a 2-bit unit by means of pull-up resistor option register H (PUOH).
Page 146: Port Function Control Registers
6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) These registers are used to set port input/output in 1-bit units.
Page 147: Port Mode Register And Output Latch Settings When Using Alternate Functions
Table 6-5. Port Mode Register and Output Latch Settings When Using Alternate Functions Pin Name P02 to P06 Note 1 Note 1 P10 to P17 P30 to P32 P33, P34 P40 to P47 P50 to P57 P120 to P127 Note 1 P130, P131 Notes 1.
Page 148: Port Mode Register Format
Figure 6-19. Port Mode Register Format Symbol PM06 PM05 PM04 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM12 PM127 PM126...
Page 149: Pull-Up Resistor Option Register Format
(2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL.
Page 150: Memory Expansion Mode Register Format
(3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-21. Memory Expansion Mode Register Format Symbol Single-chip/Memory MM2 MM1 MM0...
Page 151: Key Return Mode Register Format
(4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-22.
Page 152: Port Function Operations
6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 153: Operations On Input/Output Port
6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
Page 154 [MEMO]...
Page 155: Chapter 7 Clock Generator
CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 156: Block Diagram Of Clock Generator
Figure 7-1. Block Diagram of Clock Generator XT1/P07 Subsystem Clock Oscillator Main System Clock Scaler Oscillator STOP CHAPTER 7 CLOCK GENERATOR Prescaler MCC FRC CLS CSS PCC2 PCC1 Oscillation Mode Processor Clock Control Register Selection Register Internal Bus Watch Timer, Clock Output Function Prescaler...
Page 157: Clock Generator Control Register
7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor.
Page 158: Processor Clock Control Register Format
Figure 7-3. Processor Clock Control Register Format Symbol PCC2 PCC1 PCC0 Other than above Setting prohibited Main system clock Subsystem clock Internal feedback resistor used Internal feedback resistor not used Oscillation possible Oscillation stopped Notes 1. Bit 5 is Read Only. 2.
Page 159: Oscillation Mode Selection Register Format
The fastest instruction of the PD78075F and 78075FY Subseries can be executed in two clocks of the CPU clock. The relationship between the CPU clock (f Table 7-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (f = 5.0 MHz, f = 32.768 kHz : Main system clock oscillation frequency...
Page 160: Main System Clock Waveform Due To Writing To Osms
Figure 7-5. Main System Clock Waveform due to Writing to OSMS Write to OSMS (MCS Operating at f Caution 2. When writing “1” to MCS, V Remarks f : Main system clock frequency (fx or fx/2) : Main system clock oscillation frequency CHAPTER 7 CLOCK GENERATOR Max.
Page 161: System Clock Oscillator
7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.
Page 162: Subsystem Clock Oscillator
7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin.
Page 163 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Resonator with Incorrect Connection (2/2) (c) Changing high current is too near a signal line High Current (e) Signals are fetched Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.
Page 164: Scaler
7.4.3 Scaler The scaler divides the main system clock oscillator output (f 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1 : Connect to V XT2 : Leave open In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator...
Page 165: Clock Generator Operations
7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS).
Page 166: Main System Clock Operations
7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
Page 167: Subsystem Clock Operations
Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
Page 168: Maximum Time Required For Cpu Clock Switchover
Table 7-3. Maximum Time Required for CPU Clock Switchover Set Values before Switchover PCC2 PCC1 PCC0 PCC2 PCC2 PCC1 PCC0 16 instructions 8 instructions 4 instructions 4 instructions 2 instructions 2 instructions 1 instruction 1 instruction 1 instruction 1 instruction Remarks 1.
Page 169: System Clock And Cpu Clock Switching Procedure
7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching RESET Interrupt Request Signal System Clock CPU Clock Minimum Speed Operation Wait (26.2 ms : 5.0 MHz) Internal Reset Operation (1) The CPU is reset by setting the RESET signal to low level after power-on.
Page 170 [MEMO]...
Page 171: Chapter 8 16-Bit Timer/Event Counter
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Overview of the PD78058F and 78058FY Subseries On-Chip Timers This chapter describes the 16-bit timer/event counter and begins with an overview of the on-chip timers and related devices of the PD78058F and 78058FY Subseries. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency or one-shot pulse output.
Page 172: Timer/Event Counter Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operation Operation Interval timer mode External event counter Timer output PWM output Pulse width measurement Function Square-wave output One-shot pulse output Interrupt request Test input Notes 1. Watch timer can perform both watch timer and interval timer functions at the same time. 2.
Page 173: 16-Bit Timer/Event Counter Functions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output PWM output and pulse width measurement can be used at the same time.
Page 174: 16-Bit Timer/Event Counter Configuration
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 TI00 input cycle — (400 ns) (400 ns) (800 ns) (800 ns)
Page 175: Bit Timer/Event Counter Block Diagram
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-1. 16-Bit Timer/Event Counter Block Diagram Internal bus Capture/Compare Control Register 0 CRC02 CRC01 CRC00 16-Bit Capture/Compare TI01/ Register 00 (CR00) P01/INTP1 Match INTTM3 16-Bit Timer Register (TM0) Clear TI00/P00/ Note 1 INTP0 Match 16-Bit Capture/Compare TCL06 TCL05 TCL04 Register 01 (CR01)
Page 176: Bit Timer/Event Counter Output Control Circuit Block Diagram
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram PWM Pulse Output Control Circuit CRC02 INTTM01 CRC00 INTTM00 Edge TI00/P00/ Detection INTP0 Circuit ES11 ES10 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 External Interrupt Mode Register 0 Remark The circuitry enclosed by the dotted line is the output control circuit.
Page 177: Intp0/Ti00 Pin Valid Edge And Cr00 Capture Trigger Valid Edge
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0.
Page 178: 16-Bit Timer/Event Counter Control Registers
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Caution If the valid edge of the TIO0/P00 pin is input while CR01 is read, CR01 does not perform the capture operation and retains the current data. However, the interrupt request flag (PIF0) is set. (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses.
Page 179: Timer Clock Selection Register 0 Format
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Selection Register 0 Format Symbol TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 TCL03 TCL02 TCL01 TCL00 (32.768 kHz) Other than above Setting prohibited TCL06 TCL05 TCL04 TI00 (Valid edge specifiable) Watch timer output (INTTM 3) Other than above Setting prohibited...
Page 180 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.
Page 181: Bit Timer Mode Control Register Format
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4. 16-Bit Timer Mode Control Register Format Symbol TMC03 TMC02 TMC01 OVF0 TMC0 OVF0 Overflow not detected Overflow detected Operating Mode TMC03 TMC02 TMC01 Clear Mode Selection Operation stop (TM0 cleared to 0) PWM mode (free running) Free running mode Clear &...
Page 182: Capture/Compare Control Register 0 Format
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers 00, 01 (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 8-5.
Page 183: Bit Timer Output Control Register Format
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-6. 16-Bit Timer Output Control Register Format Symbol TOC0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 Cautions 1. Timer operation must be stopped before setting TOC0 (except for OSPT). 2. If LVS0 and LVR0 are read after data is set, they will be 0. 3.
Page 184: Port Mode Register 3 Format
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 value to FFH.
Page 185: External Interrupt Mode Register 0 Format
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8. External Interrupt Mode Register 0 Format Symbol ES31 ES30 ES21 ES20 ES11 ES10 INTM0...
Page 186: Sampling Clock Select Register Format
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select register (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction.
Page 187: 16-Bit Timer/Event Counter Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
Page 188: Interval Timer Configuration Diagram
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM3 TI00/P00/INTP0 Figure 8-12. Interval Timer Operation Timings Count Clock TM0 Count Value 0000 0001 Count Start CR00 INTTM00 Interval Time Remark Interval time = (N + 1) 16-Bit Timer Register (TM0) 0000 0001 0000 0001...
Page 189: Pwm Output Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time TCL06 TCL05 TCL04 MCS = 1 TI00 input cycle Setting prohibited (400 ns) (800 ns) (1.6 s) watch timer output cycle Other than above Setting prohibited Remarks 1.
Page 190: Control Register Settings For Pwm Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 PWM mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 CR00 set as compare register (c) 16-bit timer output control register (TOC0) OSPT OSPE...
Page 191: Example Of D/A Converter Configuration With Pwm Output
CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V ) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. capture/compare register 00 (CR00) value : External switching circuit reference voltage Figure 8-14.
Page 192: Ppg Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/ compare register 00 (CR00), respectively.
Page 193: Pulse Width Measurement Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.
Page 194: Configuration Diagram For Pulse Width Measurement By Free-Running Counter
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter INTTM3 TI00/P00/INTP00 Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input...
Page 195: Control Register Settings For Two Pulse Width Measurements With Free-Running Counter
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin.
Page 196 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input CR00 Captured Value INTP1 OVF0 FFFF...
Page 197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set.
Page 198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count Clock TM0 Count Value 0000 0001 TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 FFFF...
Page 199: Control Register Settings For Pulse Width Measurement By Means Of Restart
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).
Page 200: External Event Counter Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.
Page 201: External Event Counter Configuration Diagram
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram TI00 Valid Edge Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified) TI00 Pin Input TM0 Count Value 0000 0001 0002 0003 0004 0005 CR00 INTTM0 Caution When reading the external event counter count value, TM0 should be read.
Page 202: Square-Wave Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation Operates as a square wave output at the desired frequency with the count value set previously in the 16 bit capture/ conveyor register 00 (CR00) as the interval. The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1.
Page 203: Square-Wave Output Operation Timing
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing Count Clock TM0 Count Value 0000 0001 0002 CR00 INTTM00 TO0 Pin Output Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0 TI00 input cycle —...
Page 204: One-Shot Pulse Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input). (1) One-shot pulse output using software trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0 by software, a one-shot pulse is output from the TO0/P30 pin.
Page 205: Timing Of One-Shot Pulse Output Operation Using Software Trigger
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger Set 0CH to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 CR01 Set Value CR00 Set Value OSPT INTTM01 INTTM00 TO0 Pin Output Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to TMC01 to TMC03, respectively.
Page 206: Control Register Settings For One-Shot Pulse Output Operation Using External Trigger
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/ P30 pin with a TI00/P00 valid edge as an external trigger.
Page 207 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34. Timing of One-Shot Pulse Output Operation Using External Trigger (with Rising Edge Specified) Set 08H to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 CR01 Set Value CR00 Set Value TI00 Pin Input INTTM01 INTTM00...
Page 208: 16-Bit Timer/Event Counter Operating Precautions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse.
Page 209: Capture Register Data Retention Timing
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge.
Page 210: Operation Timing Of Ovf0 Flag
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. CR00 is set to FFFFH. When TM0 is counted up from FFFFH to 0000H. Figure 8-38.
Page 211: Chapter 9 8-Bit Timer/Event Counters
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.1 8-Bit Timer/Event Counter Function The on-chip 8-bit timer/event counters of the PD78058F, 78058FY Subseries have two modes: a mode in which the two 8-bit timer/event counter channels are separately used (8-bit timer/event counter mode), and a mode in which the two 8-bit timer/event counter channels are used combined as a 16-bit timer/event counter (16-bit timer/event counter mode).
Page 212: Bit Timer/Event Counter Interval Times
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counter Interval Times Minimum Interval Time MCS = 1 MCS = 0 (400 ns) (800 ns) (800 ns) (1.6 s) (1.6 s) (3.2 s)
Page 213: Bit Timer/Event Counter Square-Wave Output Ranges
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width MCS = 1 MCS = 0...
Page 214: 16-Bit Timer/Event Counter Mode
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times When 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter Minimum Interval Time MCS = 1 MCS = 0 (400 ns)
Page 215 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges When 8-Bit Timer/Event Counters are Used as 16-Bit Timer/Event Counter Minimum Pulse Width MCS = 1...
Page 216: 8-Bit Timer/Event Counter Configuration
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5. 8-Bit Timer/Event Counter Configuration Item Timer register Register Timer output Control register Note See Figure 6-9 P30 to P37 Block Diagram. Configuration 8 bits 2 (TM1, TM2)
Page 217: Bit Timer/Event Counter Block Diagram
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-1. 8-Bit Timer/Event Counter Block Diagram 8-Bit Compare Register 10 (CR10) Match /2-f 8-Bit Timer Register 1 (TM1) TI1/P33 /2-f TI2/P34 Timer Clock Select Register 1 Note Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counters 1 and 2 output control circuits 1 and 2, respectively.
Page 218: Block Diagram Of 8-Bit Timer/Event Counter Output Control Circuit 1
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 LVR1 LVS1 TOC11 INTTM1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 LVR2 LVS2 TOC15...
Page 219 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively).
Page 220: 8-Bit Timer/Event Counter Control Registers
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.3 8-Bit Timer/Event Counter Control Registers The following four types of registers are used to control the 8-bit timer/event counter. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) •...
Page 221: Timer Clock Select Register 1 Format
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-4. Timer Clock Select Register 1 Format Symbol TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 TCL13 TCL12 TCL11 TCL10 TI1 falling edge TI1 rising edge Other than above Setting prohibited TCL17 TCL16 TCL15 TCL14 TI2 falling edge TI2 rising edge Other than above...
Page 222: Bit Timer Mode Control Register Format
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H.
Page 223: Bit Timer Output Control Register Format
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2.
Page 224: Port Mode Register 3 Format
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 225: 8-Bit Timer/Event Counter Operation
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.4 8-Bit Timer/Event Counter Operation 9.4.1 8-bit timer/event counter mode (1) Interval timer operations Operates as an interval timer which generates interrupt requests repeatedly with the count values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval. When the count values of the 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.
Page 226: Bit Timer/Event Counter 1 Interval Time
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 TI1 input cycle TI1 input cycle (400 ns) (800 ns) (1.6 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s) (51.2 s) (102.4 s)
Page 227: Bit Timer/Event Counter 2 Interval Time
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time Minimum Interval Time TCL17 TCL16 TCL15 TCL14 MCS = 1 TI2 input cycle TI2 input cycle (400 ns) (800 ns) (1.6 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s) (51.2 s) (102.4 s)
Page 228: External Event Counter Operation Timings (With Rising Edge Specified)
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1) is input.
Page 229: Bit Timer/Event Counter Square-Wave Output Ranges
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval. The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1.
Page 230: 16-Bit Timer/Event Counter Mode
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-10. Square-Wave Output Operation Timing Count Clock TM1 Count Value Count Start CR10 Note Note The initial value of TO1 output can be set with bits 2 and 3 (LVR1 and LVS1) of the 8-bit timer output control register (TOC1).
Page 231: Interval Timer Operation Timing
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-11. Interval Timer Operation Timing Count Clock TMS (TM1, TM2) Count Value 0000 0001 Count Start CR10, CR20 INTTM2 Interval Time Remark Interval time = (N + 1) Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output control circuit 1 is inverted.
Page 232 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-9. Interval Times When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) Minimum Interval Time TCL13 TCL12 TCL11 TCL10 MCS = 1 TI1 input cycle TI1 input cycle (400 ns) (800 ns) (1.6 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s)
Page 233: External Event Counter Operation Timings (With Rising Edge Specified)
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2- channel 8-bit timer registers 1 and 2 (TM1 and TM2). Each time TM1 overflows, the overflow signal is used as a counter clock and TM2 is incremented.
Page 234: Tm1 And Tm2) Are Used As 16-Bit Timer/Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation as a Square Wave Output Operates as a square wave output at the desired frequency with the values set previously in the 8 bit conveyor registers 10 and 20 (CR10, CR20) as the interval. When setting the count value, the value of the upper 8 bits is set in CR20 and the value of the lower 8 bits is set in CR10.
Page 235: Square-Wave Output Operation Timing
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-13. Square-Wave Output Operation Timing Count Clock N + 1 CR10 CR20 Count Start 00H 01H M – 1 Interval Time Level Inversion Counter Clear...
Page 236: Cautions On 8-Bit Timer/Event Counters
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.5 Cautions on 8-Bit Timer/Event Counters (1) Timer start errors An error of one clock maximum may occur concerning the time required for a match signal to be generated after timer start. This is because the 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously with the count pulse.
Page 237: Timing After Compare Register Change During Timer Count Operation
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0.
Page 238 [MEMO]...
Page 239: Chapter 10 Watch Timer
10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals.
Page 240: Watch Timer Configuration
10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Counter Control register 10.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer. • Timer clock select register 2 (TCL2) •...
Page 241: Watch Timer Block Diagram
Figure 10-1. Watch Timer Block Diagram TMC21 Clear Prescaler TCL24 Timer Clock Select Register 2 CHAPTER 10 WATCH TIMER 5-Bit Counter Clear TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch Timer Mode Control Register Internal Bus INTWT INTTM3 To 16-Bit Timer/ Event Counter...
Page 242: Timer Clock Select Register 2 Format
Figure 10-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL24 TCL2 TCL22 TCL21 TCL20 TCL24 (39.1 kHz) (32.768 kHz) TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1.
Page 243: Watch Timer Mode Control Register Format
(2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H.
Page 244: Watch Timer Operations
10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1.
Page 245: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode An inadvertent program loop (runaway) is detected.
Page 246: Interval Times
(2) Interval timer mode Interrupt requests are generated at the preset time intervals. Interval Time Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. MCS : Bit 0 of oscillation mode selection register (OSMS) 4.
Page 247: Watchdog Timer Configuration
11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Control register Figure 11-1. Watchdog Timer Block Diagram Prescaler TCL22 TCL21 TCL20 Timer Clock Select Register 2 CHAPTER 11 WATCHDOG TIMER Configuration Timer clock select register 2 (TCL2) Watchdog timer mode control register (WDTM) Internal Bus...
Page 248: Watchdog Timer Control Registers
11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory manipulation instruction.
Page 249: Timer Clock Select Register 2 Format
Figure 11-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL24 TCL2 TCL22 TCL21 TCL20 TCL24 (39.1 kHz) (32.768 kHz) TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1.
Page 250: Watchdog Timer Mode Register Format
(2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register Format Symbol WDTM4 WDTM3...
Page 251: Watchdog Timer Operations
11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).
Page 252: Interval Timer Operation
11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generate interrupt request repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time) can be selected by the bits 0 through 2 (TCL20 through TCL22) of the timer clock select register 2 (TCL2).
Page 253: Chapter 12 Clock Output Control Circuit
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin.
Page 254: Clock Output Control Circuit Configuration
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Control register Figure 12-2. Clock Output Control Circuit Block Diagram CLOE TCL03 TCL02 TCL01 TCL00 Timer Clock Select Register 0 12.3 Clock Output Function Control Registers...
Page 255: Timer Clock Select Register 0 Format
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Figure 12-3. Timer Clock Select Register 0 Format Symbol CLOE TCL06 TCL05 TCL04 TCL03 TCL0 TCL03 TCL02 TCL01 TCL00 (32.768 kHz) Other than above Setting prohibited TCL06 TCL05 TCL04 TI00 (Valid edge specifiable) Watch Timer Output (INTTM3) Other than above Setting prohibited CLOE...
Page 256: Port Mode Register 3 Format
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f : Main system clock frequency (f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.
Page 257: Chapter 13 Buzzer Output Control Circuit
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency.
Page 258: Buzzer Output Function Control Registers
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.
Page 259: Timer Clock Select Register 2 Format
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Symbol TCL27 TCL26 TCL25 TCL24 TCL2 TCL22 TCL21 TCL20 TCL24 (39.1 kHz) (32.768 kHz) TCL27 TCL26 TCL25 Buzzer output disable Setting prohibited Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1.
Page 260: Port Mode Register 3 Format
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 261: Chapter 14 A/D Converter
14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).
Page 262: A/D Converter Configuration
14.2 A/D Converter Configuration The A/D converter consists of the following hardware. Table 14-1. A/D Converter Configuration Item Analog input Control register Register CHAPTER 14 A/D CONVERTER Configuration 8 Channels (ANI0 to ANI7) A/D converter mode register (ADM) A/D converter input select register (ADIS) External interrupt mode register 1 (INTM1) Successive approximation register (SAR) A/D conversion result register (ADCR)
Page 263: A/D Converter Block Diagram
Figure 14-1. A/D Converter Block Diagram Internal Bus A/ D Converter Input Select Register ADIS3 ADIS2 ADIS1 ADIS0 ANI0/P10 ANI1/P11 ANI2/P12 Note 1 Note 2 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 ADM1 to ADM3 Edge INTP3/P03 Detector Note 3 ES40, ES41 Trigger Enable TRG FR1 FR0 ADM3 ADM2 ADM1 A/D Converter Mode Register...
Page 264 (1) Successive approximation register (SAR) The analog input voltage value and the voltage tap (comparative voltage) value from the serial resistance string are compared and the results are stored in this register from the most significant bit (MSB). If values are stored to the least significant bit (LSB) (after A/D conversion), the contents of the SAR are transferred to the A/D conversion results register (ADCR).
Page 265: A/D Converter Control Registers
(7) AV REF0 This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV and AV The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AV pin to AV level in standby mode.
Page 266: A/D Converter Mode Register Format
Figure 14-2. A/D Converter Mode Register Format Symbol ADM3 ADM3 ADM2 ADM1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 MCS = 1 80/f Setting prohibited 40/f Setting prohibited 50/f Setting prohibited 100/f (20.0 s) Other than above Setting prohibited No external trigger (software starts) Conversion started by external trigger (hardware starts) Operation stop...
Page 267: A/D Converter Input Select Register Format
(2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H.
Page 268: External Interrupt Mode Register 1 Format
(3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-4. External Interrupt Mode Register 1 Format Symbol ES71 ES70...
Page 269: A/D Converter Operations
14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).
Page 270: A/D Converter Basic Operation
Figure 14-5. A/D Converter Basic Operation Sampling Time A/D Converter Sampling Operation Undefined ADCR INTAD A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the beginning.
Page 271: Input Voltage And Conversion Results
14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( 256 + 0.5) REF0...
Page 272: A/D Converter Operating Mode
14.4.3 A/D converter operating mode Select 1 analog input channel from ANI0-ANI7 by the A/D converter input select register (ADIS) and the A/D converter mode register (ADM) and begin A/D conversion. The following two methods are used for starting an A/D conversion operation. •...
Page 273: A/D Conversion By Software Start
(2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
Page 274: A/D Converter Cautions
14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV be cut in order to minimize the overall system power dissipation.
Page 275: Connection Of Analog Input Pin
(3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-10 in order to reduce noise. Figure 14-10.
Page 276: A/D Conversion End Interrupt Request Generation Timing
(6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and ADIF for the analog input before the change may be set just before the ADM rewrite.
Page 277 (7) AV The AV pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to ANI7/P17. Therefore, be sure to apply the same voltage as V so as to switch to a backup battery. Figure 14-12.
Page 278 [MEMO]...
Page 279: Chapter 15 D/A Converter
15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. D/A conversion is started by setting the DACE0 and DACE1 of the D/A converter mode register (DAM). There are two types of modes for the D/A converter, as follows.
Page 280: D/A Converter Configuration
15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Register Control register Figure 15-1. D/A Converter Block Diagram DACS1 Write INTTM2 DACS0 Write INTTM1 REF1 DAM5 DAM4 DACE1 DACE0 D/A Converter Mode Register Internal Bus CHAPTER 15 D/A CONVERTER Configuration...
Page 281 (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers where values are set for determining the analog voltage output respectively to pins ANO0 and ANO1. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input sets these registers to 00H.
Page 282: D/A Converter Control Registers
15.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 15-2.
Page 283: Operations Of D/A Converter
15.4 Operations of D/A Converter (1) Select the operation mode for channel 0 using bit 4 (DAM4) of the D/A converter mode register (DAM), and select the operation mode for channel 1 using bit 5 (DAM5). (2) Set data corresponding to the analog voltage values output respectively to pins ANO0/P130 and ANO1/P131 in D/A conversion setting registers 0 and 1 (DACS0 and DACS1).
Page 284: Cautions Related To D/A Converter
15.5 Cautions Related to D/A Converter (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins.
Page 285: Chapter 16 Serial Interface Channel 0 ( Pd78058F Subseries)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) The PD78058F Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
Page 286: Serial Interface Channel 0 Functions
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). The SBI mode is compatible with the NEC Serial Bus Format and sends and receives data distinguishing between 3 different types, “Address”, “Command” and “Data”.
Page 287: Serial Bus Interface (Sbi) System Configuration Example
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level.
Page 288: Serial Interface Channel 0 Configuration
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2. Serial Interface Channel 0 Configuration Item Register Control register Note See Figure 6-5 P20, P21, P23 to P26 Block Diagram and Figure 6-6 P22 and P27 Block Diagram. Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA)
Page 289: Serial Interface Channel 0 Block Diagram
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Figure 16-2. Serial Interface Channel 0 Block Diagram Serial Operating Mode Register 0 CSIM CSIE0 COI WUP Control Circuit SI0/SB0/ PM25 Output Latch Output Control SO0/SB1/ PM26 Output Control P26 Output Latch SCK0/ PM27 Output...
Page 290 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.
Page 291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (3) SO0 latch This latch holds the SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
Page 292: Serial Interface Channel 0 Control Registers
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...
Page 293: Timer Clock Select Register 3 Format
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Figure 16-3. Timer Clock Select Register 3 Format Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 Other than above Setting prohibited TCL37 TCL36 TCL35 TCL34 Other than above Setting prohibited Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Page 294: Serial Operating Mode Register 0 Format
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Page 295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Figure 16-4. Serial Operating Mode Register 0 Format (2/2) Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data...
Page 296: Serial Bus Interface Control Register Format
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 16-5.
Page 297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Figure 16-5. Serial Bus Interface Control Register Format (2/2) ACKE Acknowledge signal automatic output disable (output with ACKT enable) Acknowledge signal is output in synchronization with the 9th clock Before completion of transfer falling edge of SCK0 (automatically output when ACKE = 1).
Page 298: Interrupt Timing Specify Register Format
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Page 299: Serial Interface Channel 0 Operations
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode •...
Page 300: 3-Wire Serial I/O Mode Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Symbol CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 CSIM00 Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM...
Page 302 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.
Page 303: Wire Serial I/O Mode Timings
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
Page 304: Circuit Of Switching In Transfer Bit Order
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 305: Sbi Mode Operation
16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function.
Page 306 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available.
Page 307: Sbi Transfer Timings
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”. Figure 16-11 shows the address, command, and data transfer timings.
Page 308: Bus Release Signal
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device.
Page 309: Addresses
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses SCK0 SB0 (SB1) Bus Release...
Page 310: Commands
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands SCK0 SB0 (SB1) Command Command Signal Figure 16-17. Data SCK0 SB0 (SB1) Data...
Page 311: Acknowledge Signal
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] SCK0 SB0 (SB1) [When output in synchronization with 9th clock SCK0] SCK0...
Page 312: Busy And Ready Signals
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is intended to report to the master device that the slave device is ready for data transmission/reception.
Page 313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Symbol CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 CSIM00 Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM...
Page 314 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the SBI mode. Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Used for bus release signal output.
Page 315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) ACKD Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution. • When CSIE0 = 0 • When RESET input is applied Note BSYE Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after...
Page 316 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol SINT SIC SVAM Caution Be sure to set bits 0 to 3 to 0. Notes 1.
Page 317: Relt, Cmdt, Reld, And Cmdd Operations (Master)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (4) Various signals Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in SBI. Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master) SIO0 SCK0 SB0 (SB1)
Page 318: Ackt Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Figure 16-22. ACKT Operation SCK0 ACK signal is output for SB0 (SB1) a period of one clock just after setting ACKT When set during this period Caution Do not set ACKT before termination of transfer.
Page 319: Acke Operations
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Figure 16-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer SCK0 SB0 (SB1) ACKE (b) When set after completion of transfer SCK0 SB0 (SB1) ACKE (c) When ACKE = 0 upon completion of transfer SCK0 SB0 (SB1) ACKE...
Page 320: Ackd Operations
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (a) When ACK signal is output at 9th clock of SCK0 SIO0 SCK0 SB0 (SB1) ACKD (b) When ACK signal is output after 9th clock of SCK0 SIO0 SCK0 SB0 (SB1) ACKD (c) Clear timing when transfer start is instructed in BUSY SIO0...
Page 321: Various Signals In Sbi Mode
Output Signal Name Definition Device Bus release SB0 (SB1) rising edge Master signal when SCK0 = 1 (REL) Command SB0 (SB1) falling edge signal Master when SCK0 = 1 (CMD) Low-level signal to be output to SB0 (SB1) during Acknowledge Master/ one-clock period of SCK0 signal...
Page 322 Output Signal Name Definition Device Synchronous clock to output address/command/ data, ACK signal, synchro- Serial clock Master nous BUSY signal, etc. (SCK0) Address/command/data are transferred with the first eight synchronous clocks. 8-bit data to be transferred Address in synchronization with Master (A7 to A0) SCK0 after output of REL...
Page 323: Pin Configuration
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ... Serial clock input/output pin <1> Master .. CMOS and push-pull output <2>...
Page 324 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master coincides with the address set to SVA when the wake-up function specify bit (WUP) = 1.
Page 325: Address Transmission From Master Device To Slave Device (Wup = 1)
Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter) CMDT RELT CMDT Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing CMDD CMDD CMDD Hardware Operation Clear RELD...
Page 326: Command Transmission From Master Device To Slave Device
Figure 16-28. Command Transmission from Master Device to Slave Device Master Device Processing (Transmitter) CMDT Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing CMDD Hardware Operation Write to SIO0 Serial Transmission Command Serial Reception Interrupt Servicing...
Page 327: Data Transmission From Master Device To Slave Device
Figure 16-29. Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Program Processing Hardware Operation Transfer Line SCK0 Pin SB0 (SB1) Pin Slave Device Processing (Receiver) Program Processing Hardware Operation Write to SIO0 Serial Transmission Data Serial Reception Interrupt Servicing (Preparation for the Next Serial Transfer) INTCSI0...
Page 328: Data Transmission From Slave Device To Master Device
Figure 16-30. Data Transmission from Slave Device to Master Device Master Device Processing (Receiver) Program Processing SCK0 Hardware Operation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY Slave Device processing (Transmitter) Write Program Processing to SIO0 BUSY Hardware Operation Clear FFH Write to SIO0...
Page 329 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...
Page 330 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (10) How to determine the slave busy state When a device is in the master mode, use the following procedure to determine if the slave is in the busy state or not. <1>...
Page 331: 2-Wire Serial I/O Mode Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
Page 332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) Symbol CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 CSIM00 Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM...
Page 333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.
Page 334: Wire Serial I/O Mode Timings
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
Page 335: Relt And Cmdt Operations
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
Page 336: Sck0/P27 Pin Output Manipulation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES) 16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to be controlled with the RELT and CMDT bits of serial bus interface control register (SBIC).) SCK0/P27 pin output manipulating procedure is described below.
Page 337: Chapter 17 Serial Interface Channel 0 ( Pd78058Fy Subseries)
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) The PD78058FY Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
Page 338: Serial Interface Channel 0 Functions
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I C (Inter IC) bus mode Caution Do not switch the operating mode (3-wire serial I/O/ 2-wire serial I/O/I serial interface channel 0 is enabled.
Page 339 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (4) I C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received.
Page 340: Serial Interface Channel 0 Configuration
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Register Control register Note See Figure 6-7 P20, P21, P23 to P26 Block Diagram and Figure 6-8 P22 and P27 Block Diagram. Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA)
Page 341: Serial Interface Channel 0 Block Diagram
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-2. Serial Interface Channel 0 Block Diagram Serial Operating Mode Register 0 CSIM CSIE0 COI WUP BSYE Control Circuit SI0/SB0/ SDA0/P25 PM25 Output Latch Output Control SO0/SB1/ SDA1/P26 PM26 Output Control P26 Output Latch SCK0/...
Page 342 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.
Page 343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (3) SO0 latch This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by software. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
Page 344: Serial Interface Channel 0 Interrupt Request Signal Generation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Table 17-3. Serial Interface Channel 0 Interrupt Request Signal Generation Serial Transfer mode BSYE WUP WAT1 WAT0 ACKE 3-wire or 2-wire serial I/O mode Other than above C bus mode (transmit) Other than above C bus mode (receive) Other than above...
Page 345: Serial Interface Channel 0 Control Registers
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...
Page 346: Timer Clock Select Register 3 Format
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-3. Timer Clock Select Register 3 Format Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 Other than above Setting prohibited TCL37 TCL36 TCL35 TCL34 Other than above Setting prohibited Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Page 347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Page 348: Serial Operating Mode Register 0 Format
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-4. Serial Operating Mode Register 0 Format Symbol CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 CSIM00 Input Clock to SCK0/SCL pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM...
Page 349: Serial Bus Interface Control Register Format
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 17-5.
Page 350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-5. Serial Bus Interface Control Register Format (2/2) ACKE Disables acknowledge signal automatic output. (However, output with ACKT is enabled) Used for reception when 8-clock wait mode is selected or for transmission. Enables acknowledge signal automatic output.
Page 351: Interrupt Timing Specify Register Format
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Page 352 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-6. Interrupt Timing Specify Register Format (2/2) SVAM Bits 0 to 7 Bits 1 to 7 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer Low level High level Notes 1.
Page 353: Serial Interface Channel 0 Operations
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode •...
Page 354: 3-Wire Serial I/O Mode Operation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.
Page 356: Wire Serial I/O Mode Timings
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
Page 357: Circuit Of Switching In Transfer Bit Order
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 358: 2-Wire Serial I/O Mode Operation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
Page 359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Symbol CSIM0 CSIE0 COI CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 CSIM00 Input Clock to SCK0 pin from off-chip...
Page 360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT When RELT = 1, SO0 Iatch is set to 1.
Page 361: Wire Serial I/O Mode Timings
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
Page 362: Relt And Cmdt Operations
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
Page 363: I 2 C Bus Mode Operation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.4.4 I C bus mode operation The I C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data bus (SDA0 or SDA1) line.
Page 364 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (1) I C bus mode functions In the I C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.
Page 365: Start Condition
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer.
Page 366: Stop Condition
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer.
Page 367: Wait Signal
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers.
Page 368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (3) Register setting The I C bus mode is set by the serial operating mode register 0 (CSIM0), serial bus interface control register (SBIC), and interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT Use for stop condition output.
Page 370 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol SINT SVAM CLC WREL WAT1 WAT0 WAT1 WAT0 Interrupt service request is generated on rise of 8th SCK0 clock cycle (clock output is high impedance).
Page 371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (4) Various signals A list of signals in the I C bus mode is given in Table 17-4. Table 17-4. Signals in I Signal Name Start condition Definition : Function : Signaled by : Signaled when : Affected flag(s) : CMDD (is set.)
Page 372: Pin Configuration
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1>...
Page 373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (7) Error detection In the I C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device.
Page 374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1/3) Master Device Operation SIO0 Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0 Transfer Line SDA0 Slave Device Operation...
Page 375: Data Transmission From Master To Slave (Both Master And Slave Selected 9-Clock Wait)
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (2/3) Master Device Operation SIO0 Address Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0 Transfer Line 2 3 4 5 6 7 8...
Page 376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (3/3) Master Device Operation SIO0 Data Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0 Transfer Line 2 3 4 5 6 7 8...
Page 377: Data Transmission From Slave To Master (Both Master And Slave Selected 9-Clock Wait)
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address Master Device Operation SIO0 Address Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT...
Page 378 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (2/3) Master Device Operation SIO0 Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0 Transfer Line 2 3 4 5 6 7 8 SDA0...
Page 379 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop Condition Master Device Operation SIO0 Write SIO0 ACKD CMDD RELD BSYE ACKE CMDT RELT WREL INTCSI0...
Page 380: Cautions On Use Of I C Bus Mode
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.4.5 Cautions on use of I C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal.
Page 381: Slave Wait Release (Transmission)
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or execution of an serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line.
Page 382: Slave Wait Release (Reception)
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (3) Slave wait release (slave reception) The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register (SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed. When the slave receives data, the first bit of the data sent from the master may not be received if the SCL line immediately goes into a high-impedance state after an instruction that writes data to SIO has been executed.
Page 383: Restrictions In I 2 C Bus Mode
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1). This is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore, the wake-up condition cannot be used when the slave receives the undefined number of data from the master.
Page 384 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.7; <7> CLR1 P2.5; <8>...
Page 385: Sck0/Scl/P27 Pin Output Manipulation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of serial clocks can also be arbitrarily set by software (the SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)).
Page 386: Logic Circuit Of Scl Signal
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES) Figure 17-29. Logic Circuit of SCL Signal CLC (manipulated by bit manipulation instruction) Wait request signal Serial clock (low while transfer is stopped) Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit. 2.
Page 387: Chapter 18 Serial Interface Channel 1
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
Page 388: Serial Interface Channel 1 Configuration
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1. Serial Interface Channel 1 Configuration Item Register Control register Note See Figure 6-5 and Figure 6-7 P20, P21, P23 to P26 Block Diagram and Figure 6-6 and Figure 6-8 P22 and P27 Block Diagram.
Page 389: Serial Interface Channel 1 Block Diagram
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1. Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit/Receive Buffer RAM Address Pointer (ADTP) ADTI ADTI Serial I/O SI1/ Shift Register 1 (SIO1) PM21 SO1/ P21 Output Latch PM23 STB/ Hand- shake BUSY/...
Page 390 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.
Page 391: Serial Interface Channel 1 Control Registers
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) •...
Page 392: Timer Clock Select Register 3 Format
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-2. Timer Clock Select Register 3 Format Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 TCL37 TCL36 TCL35 TCL34 Other than above Setting prohibited Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand. Remarks 1.
Page 393: Serial Operating Mode Register 1 Format
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Page 394: Automatic Data Transmit/Receive Control Register Format
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
Page 395: Automatic Data Transmit/Receive Interval Specify Register Format
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 18-5.
Page 396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
Page 397 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 No control of interval by ADTI Control of interval by ADTI (ADTI0 to ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Notes 1.
Page 398 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4) Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
Page 399: Serial Interface Channel 1 Operations
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.
Page 400: 3-Wire Serial I/O Mode Operation
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers that incorporate a conventional synchronous serial interface such as the 75X/XL, 78K and 17K Series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1).
Page 401: Wire Serial I/O Mode Timings
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock SCK1. The transmit data is held in the SO1 latch and is output from the SO1 pin.
Page 402: Circuit Of Switching In Transfer Bit Order
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-7. Circuit of Switching in Transfer Bit Order Internal Bus LSB-first MSB-first Read/Write Gate Serial I/O Shift Register 1 (SIO1) SCK1 Start bit switching is realized by switching the bit order write to SIO1. The SIO1 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to SIO1.
Page 403: 3-Wire Serial I/O Mode Operation With Automatic Transmit/Receive Function
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
Page 404 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol CSIM1 CSIE1 DIR CSIM11 CSIM10 Clock externally input to SCK1 pin 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3) 3-wired serial I/O mode 3-wired serial I/O mode with automatic transmit/receive function Start Bit PM20...
Page 405 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Symbol ADTC ARLD ERCE ERR TRF STRB Notes 1. Bits 3 and 4 (TRF and ERR) are Read-Only bits. 2.
Page 406 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0...
Page 407 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f is 2/f Minimum = (n+1)
Page 408 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 No control of interval by ADTI Control of interval by ADTI (ADTI0 to ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Notes 1. The interval is dependent only on CPU processing. 2.
Page 409 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expressions is smaller than 2/f is 2/f Minimum = (n+1)
Page 410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of internal buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address.
Page 411: Basic Transmission/Reception Mode Operation Timings
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1.
Page 412: Basic Transmission/Reception Mode Flowchart
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9. Basic Transmission/Reception Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
Page 413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, internal buffer RAM operates as follows. (i) Before transmission/reception (See Figure 18-10 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1.
Page 414 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-10. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) FADFH FAC5H Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) (c) Completion of transmission/reception...
Page 415: Basic Transmission Mode Operation Timings
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1.
Page 416: Basic Transmission Mode Flowchart
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12. Basic Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
Page 417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, internal buffer RAM operates as follows. (i) Before transmission (See Figure 18-13 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1.
Page 418 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-13. Internal Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) FADFH FAC5H Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) FADFH...
Page 419: Repeat Transmission Mode Operation Timing
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1) is set at 1.
Page 420: Repeat Transmission Mode Flowchart
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15. Repeat Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
Page 421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, internal buffer RAM operates as follows. (i) Before transmission (See Figure 18-16 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1.
Page 422 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-16. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes FADFH FAC5H Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) FAC0H...
Page 423: Automatic Transmission/Reception Suspension And Restart
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0. It is suspended upon completion of 8-bit data transfer.
Page 424: System Configuration When The Busy Control Option Is Used
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving. (a) Busy control option Busy control is a function which causes the master device’s serial transmission to wait when the slave device outputs a busy signal to the master device, and maintain the wait state while that busy signal is...
Page 425: Operation Timings When Using Busy Control Option (Busy0 = 0)
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19. Caution Busy control cannot be used at the same time as interval timing control using the auto data send and receive interval instruction register (ADIT).
Page 426: Busy Signal And Wait Cancel (When Busy0 = 0)
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20 Busy Signal and Wait Cancel (When BUSY0 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY In the case where the busy (Active High) signal becomes inactive directly when sampled...
Page 427: Operation Timings When Using Busy & Strobe Control Option (Busy0 = 0)
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-21. Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0) SCK1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY CSIIF1 Caution When TRF is cleared, the SO1 pin becomes low level. Remarks CSIIF1: Interrupt request flag : Bit 3 of the auto data send and receive control register (ADTC) D7 D6 D5 D4 D3 D2 D1 D0...
Page 428 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the strobe control option is not used, this bit slippage will have an effect on sending of the next byte.
Page 429: Automatic Transmit/Receive Interval Time
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive.
Page 430: Operation Timing With Automatic Data Transmit/Receive Function Performed By Internal Clock
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the auto send and receive function is operated by the internal clock, interval timing by CPU processing is as follows.
Page 431: Interval Timing Through Cpu Processing (When The External Clock Is Operating)
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is set. When the automatic transmit/receive function is used by the external clock, it must be selected so that the interval may be longer than the values shown as follows.
Page 432 [MEMO]...
Page 433: Chapter 19 Serial Interface Channel 2
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
Page 434: Serial Interface Channel 2 Configuration
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1. Serial Interface Channel 2 Configuration Item Register Control register Note See Figure 6-15 P70 Block Diagram and Figure 6-16 P71 and P72 Block Diagram. Configuration Transmit shift register (TXS) Receive shift register (RXS)
Page 435: Serial Interface Channel 2 Block Diagram
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-1. Serial Interface Channel 2 Block Diagram Receive Buffer Register (RXB/SIO2) Direction Control Circuit Receive Shift RxD/SI2/ Register (RXS) TxD/SO2/ PM71 Reception Control Circuit PM72 ASCK/ SCK2/P72 CSIE2 Serial Operating Mode Register 2 Note See Figure 19-2 for the baud rate generator configuration.
Page 436: Baud Rate Generator Block Diagram
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-2. Baud Rate Generator Block Diagram CSIE2 Transmit Clock Receive Clock Start Bit Detection Start Bit Sampling Clock 5-Bit Counter Match MDL0 to MDL3 Decoder Match 5-Bit Counter TPS3 TPS2 TPS1 TPS0 Baud Rate Generator Control Register Internal Bus ASCK/SCK2/P72...
Page 437 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation.
Page 438: Serial Interface Channel 2 Control Registers
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial operating mode register 2 (CSIM2) • Asynchronous serial interface mode register (ASIM) • Asynchronous serial interface status register (ASIS) •...
Page 439: Asynchronous Serial Interface Mode Register Format
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H.
Page 440: Serial Interface Channel 2 Operating Mode Settings
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72 TXE RXE SCK CSIE2 CSIM22 CSCK Other than above (2) 3-wire Serial I/O Mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72...
Page 441: Asynchronous Serial Interface Status Register Format
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of the ASIS are undefined.
Page 442: Baud Rate Generator Control Register Format
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 19-6. Baud Rate Generator Control Register Format (1/2) Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0...
Page 443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-6. Baud Rate Generator Control Register Format (2/2) TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution If data is written to BRGC during the communication operation, the baud rate generator output is disrupted and communication cannot be performed normally. Therefore, do not write data to BRGC during a communication operation.
Page 444: Relationship Between Main System Clock And Baud Rate
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock.
Page 445: Relationship Between Asck Pin Input Frequency And Baud Rate (When Brgc Is Set To 00H)
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = (k+16)
Page 446: Serial Interface Channel 2 Operation
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
Page 447 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol ASIM Address After Reset ISRM SCK FF70H Receive Operation Control Receive operation stopped Receive operation enabled Transmit Operation Control...
Page 448: Asynchronous Serial Interface (Uart) Mode
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
Page 449 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. Symbol ASIM Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port.
Page 450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. Symbol ASIS Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read.
Page 451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 : 5-bit counter source clock : Value set in MDL0 to MDL3 (0 Address...
Page 452 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Caution If data is written to BRGC during a communication operation, the baud rate generator output is disrupted and communication cannot be performed normally. Therefore, do not write data to BRGC during a communication operation. Remarks 1.
Page 453: Relationship Between Main System Clock And Baud Rate
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock.
Page 454: Relationship Between Asck Pin Input Frequency And Baud Rate (When Brgc Is Set To 00H)
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = (k+16)
Page 455: Asynchronous Serial Interface Transmit/Receive Data Format
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format Start 1 data frame is composed of each of the bits shown below. •...
Page 456 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 457: Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated.
Page 458: Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. When the RxD pin input becomes low, the baud rate generator’s 5 bit counter (see Figure 19-2) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output.
Page 459: Receive Error Timing
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and at the same time a receive error interrupt request (INTSER) is generated.
Page 460: Receive Buffer Register (Rxb) Status And Receive Completion Interrupt Request (Intsr Generation When Receiving Is Terminated
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) If bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared to (0) during transmission and sending operation is halt, be sure to set the transmit shift register (TXS) to FFH, then set TXE to 1 before executing the next transmission.
Page 461: 3-Wire Serial I/O Mode
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
Page 462 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. Symbol ASIM Address...
Page 463 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 : 5-bit counter source clock : Value set in MDL0 to MDL3 (0 Address...
Page 464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Other than above Setting prohibited Note If data is written to BRGC during a communication operation, the baud rate generator output is disrupted and communication cannot be performed normally. Therefore, do not write data to BRGC during a communication operation. Remarks 1.
Page 465 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 to TPS3.
Page 466: Wire Serial I/O Mode Timing
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2.
Page 467: Circuit Of Switching In Transfer Bit Order
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 468: Restrictions On Using Uart Mode
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Restrictions on using UART mode In the UART mode, a receive completion interrupt request (INTSR) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (INTSER). Thereby, the phenomenon shown below may occur.
Page 469: Period That Reading Receive Buffer Register Is Prohibited
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-15. Period that Reading Receive Buffer Register Is Prohibited RxD (Input) START INTSR INTSER (when Framing or Overrun Error is Generated) INTSER (when Parity Error is Generated) T1 : The amount of time for one unit of data sent in the baud rate selected with the baud rate generator control register (BRGC) (1/baud rate) T2 : The amount of time for 2 clocks of 5-bit counter source clock (f BRGC...
Page 470 [Example] INTSER is Generated 7 Clocks (MIN.) of CPU Clock (Time from Interrupt Request to Servicing) CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Main Processing UART Receive Error Interrupt (INTSER) Servicing Instructions for 2205 clocks (MIN.) of CPU clock are required. MOV A,RXB RETI...
Page 471: Chapter 20 Real-Time Output Port
CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally. This is called the real-time output function.
Page 472: Real-Time Output Port Block Diagram
20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1. Real-time Output Port Configuration Item Register Control register Figure 20-1. Real-time Output Port Block Diagram Real-time Output Port Control Register EXTR BYTE INTP2 Output Trigger INTTM1 Control Circuit INTTM2...
Page 473: Real-Time Output Buffer Register Configuration
CHAPTER 20 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown in Figure 20-2. When specifying 4 bits 2 channels as the operating mode, data are set individually in RTBL and RTBH. When specifying 8 bits 1 channel as the operating mode, data are set to both RTBL and RTBH by writing 8-bit data to either RTBL or RTBH.
Page 474: Real-Time Output Port Control Registers
CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output mode of port 12 pins (P120 to P127) which are multiplexed with real- time output pins (RTP0 to RTP7).
Page 475: Real-Time Output Port Control Register Format
CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 476 [MEMO]...
Page 477: Chapter 21 Interrupt And Test Functions
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.
Page 478: Interrupt Sources And Configuration
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.2 Interrupt Sources and Configuration Combining all the factors in interrupts, non-maskable interrupts, maskable interrupts and software interrupts, there are a total of 22 source (see Table 21-1). Table 21-1. Interrupt Source List (1/2) Note 1 Interrupt Default...
Page 479 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1. Interrupt Source List (2/2) Note 1 Interrupt Default Type Priority Name INTTM3 Reference time interval signal from watch timer INTTM00 Generation of 16-bit timer register, capture/compare register (CR00) match signal INTTM01 Generation of 16-bit timer register, Maskable capture/compare register (CR01) match signal...
Page 480: Basic Configuration Of Interrupt Function
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Interrupt Request (B) Internal maskable interrupt Interrupt Request (C) External maskable interrupt (INTP0) Sampling Clock External Interrupt Mode Select Register Register (INTM0) (SCS) Sampling Edge...
Page 481 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) External Interrupt Mode Register (INTM0, INTM1) Interrupt Edge Request Detector (E) Software interrupt Interrupt Request Remark Interrupt request flag Interrupt enable flag ISP : Inservice priority flag MK :...
Page 482: Interrupt Function Control Registers
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) •...
Page 483: Interrupt Request Flag Register Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 484: Interrupt Mask Flag Register Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
Page 485: Priority Specify Flag Register Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
Page 486: External Interrupt Mode Register 0 Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP6. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 21-5.
Page 487: External Interrupt Mode Register 1 Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-6. External Interrupt Mode Register 1 Format Symbol INTM1 ES71 ES70 ES61 ES60 ES51 After Address Reset ES50 ES41 ES40 FFEDH ES41 ES40 Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 ES50 Falling edge...
Page 488: Sampling Clock Select Register Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is removed with sampling clocks. SCS is set with an 8-bit memory manipulation instruction.
Page 489: Noise Elimination Circuit Input/Output Timing (During Rising Edge Detection)
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS The noise elimination circuit sets the interrupt request flag (PIF0) at (1) when the sampled INTP0 input level is active twice in succession. Figure 21-8 shows the input/output timing of the noise elimination circuit. Figure 21-8.
Page 490: Program Status Word Format
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.
Page 491: Interrupt Servicing Operations
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt acknowledge operation A non-maskable interrupt request is received without condition even when in the interrupt request reception prohibited state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the program status word (PSW) and then program counter (PC), the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched.
Page 492: Flowchart From The Time A Non-Maskable Interrupt Request Is Generated Until It Is Received
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-10. Flowchart from the Time a Non-maskable Interrupt Request Is Generated Until It Is Received Interrupt request generation WDTM Figure 21-11. Non-Maskable Interrupt Request Acknowledge Timing CPU Processing Instruction TMIF4 Interrupt requests generated during this time are received at the timing indicated by .
Page 493: Non-Maskable Interrupt Request Acknowledge Operation
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1> NMI Request <2> 1 Instruction Execution If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1>...
Page 494: Maskable Interrupt Request Reception
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable Interrupt request reception For a maskable interrupt request, the interrupt request flag is set at (1) and if the mask (MK) flag of that interrupt is cleared (0), it is possible for it to be received. A vector interrupt request is received if an interrupt enable state exists (when the IE flag is set at (1)).
Page 495: Interrupt Request Acknowledge Processing Algorithm
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13. Interrupt Request Acknowledge Processing Algorithm Interrupt request reserve Does one of the simultaneously generated XXPR=0 interrupt request have a high priority? Interrupt request reserve IE=1? Interrupt request reserve Vectored interrupt servicing XXIF : Interrupt Request Flag XXMK : Interrupt Mask Flag XXPR : Priority Order Specification Flag : Flag which controls reception of maskable interrupt requests (1 = permitted, 0 = prohibited)
Page 496: Interrupt Request Acknowledge Timing (Maximum Time)
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time) CPU Processing Instruction PR=1) PR=0) Remark 1 clock : Figure 21-15. Interrupt Request Acknowledge Timing (Maximum Time) CPU Processing Instruction PR=1) PR=0) Remark 1 clock : Instruction : CPU clock) 25 Clocks...
Page 497: Software Interrupt Request Acknowledge Operation
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is received by the execution of a BRK command. A software interrupt cannot be prohibited. If a software interrupt request is received, the contents of the program status word (PSW) and the program counter (PC) are saved to the stack in that order, the IE flag is reset (0) and the contents of the vector table (003EH, 003FH) are loaded in the PC and branched.
Page 498: Interrupt Request Enabled For Multiple Interrupt During Interrupt Servicing
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-4. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing Multiple Interrupt Request Interrupt Currently Being Processed Non-maskable interrupt ISP=0 Maskable interrupt ISP=1 Software interrupt Remarks 1. E : Multiple interrupt enable 2. D : Multiple interrupt disable 3.
Page 499: Multiple Interrupt Example
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (1/2) Example 1 Example of multiple interrupt requests being generated twice. Main Processing IE=0 INTxx INTyy (PR=1) (PR=0) During processing of interrupt INTxx, 2 interrupt requests, INTyy and INTzz, are received and multiple interrupts are generated.
Page 500 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Example 3 Example of a multiple interrupt not being generated because an interrupt was not permitted. Main Processing INTxx (PR=0) 1 Instruction Execution In processing of interrupt INTxx, interrupt reception was not permitted (the IE command was not issued), so interrupt request INTyy was not received and multiple interrupts were not generated.
Page 501: Interrupt Request Reserve
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve Among the commands, there are some for which, even if an interrupt request is generated while they are being executed, reception of the interrupt request is held until execution of the next command is completed. The commands of this type (interrupt request hold commands) are shown below.
Page 502: Test Functions
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.5 Test Functions When a clock timer overflow occurs and when the port 4 falling edge is detected, a corresponding test input flag is set (1) and a standby release signal is generated. Unlike the interrupt function, vector processing is not executed. There are two test input factors as shown in Table 21-5.
Page 503: Format Of Interrupt Request Flag Register 1L
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 21-19.
Page 504: Test Input Signal Acknowledge Operation
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
Page 505: Chapter 22 External Device Expansion Function
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe etc.
Page 506: Memory Map When Using External Device Expansion Function
Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map When Using External Device Expansion Function (1/2) (a) Memory Map of the PD78056F and 78056FY, and of the PD78P058F and 78P058FY when the internal PROM is 48 Kbytes.
Page 507 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map When Using External Device Expansion Function (2/2) PD78058F, 78058FY, 78P058F, 78P058FY Memory map when internal ROM (PROM) size is 56 Kbytes FFFFH FF00H FEFFH Internal High-Speed RAM FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM...
Page 508: External Device Expansion Function Control Register
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and also sets the input/output of port 4. MM is set with an 1-bit or 8-bit memory manipulation instruction.
Page 509: Memory Size Switching Register Format
Figure 22-3. Memory Size Switching Register Format Symbol RAM2 RAM1 RAM0 ROM3 Note The values after reset depend on the product. (See Table 22-3) Table 22-3. Values When the Memory Size Switching Register Is Reset PD78056F, 78056FY PD78058F, 78058FY After Address Reset ROM2 ROM1 ROM0 FFF0H...
Page 510: External Device Expansion Function Timing
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory.
Page 511: Instruction Fetch From External Memory
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB AD0 to AD7 Lower Address Operation Code A8 to A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower Address...
Page 512: External Memory Read Timing
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-5. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB AD0 to AD7 Lower Address Read Data A8 to A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower Address...
Page 513: External Memory Write Timing
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z AD0 to AD7 Lower Address Write Data Higher Address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower Address...
Page 514: External Memory Read Modify Write Timing
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower Address Read Data Write Data AD0 to AD7 A8 to A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Read Data...
Page 515: Chapter 23 Standby Function
CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation.
Page 516: Standby Function Control Register
23.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 517: Standby Function Operations
23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 23-1.
Page 518: Halt Mode Clear Upon Interrupt Request Generation
(2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request The HALT mode is cleared when an unmasked interrupt request is generated. If interrupt acknowledge is enabled, vectored interrupt servicing is performed. If disabled, the next address instruction is executed. Figure 23-2.
Page 519: Halt Mode Release By Reset Input
CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input The HALT mode is cleared upon RESET signal input. As is the case with normal reset operation, a program is executed after branching to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input HALT Instruction RESET...
Page 520: Stop Mode
23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V to minimize the leakage current at the crystal oscillator.
Page 521: Stop Mode Release By Interrupt Request Generation
CHAPTER 23 STANDBY FUNCTION (2) STOP mode release The STOP mode can be cleared with the following three types of sources. (a) Release by unmasked interrupt request The STOP mode is cleared upon generation of an unmasked interrupt request. If interrupt acknowledge is enabled, vectored interrupt servicing is performed after the lapse of the oscillation stabilization time.
Page 522: Release By Stop Mode Reset Input
(c) Release by RESET input The STOP mode is cleared upon RESET input, and after the lapse of the oscillation stabilization time, reset operation is performed. Figure 23-5. Release by STOP Mode RESET Input STOP Instruction RESET Signal Operating Mode STOP Mode Oscillation Clock...
Page 523: Chapter 24 Reset Function
CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal. External reset input with RESET pin Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 524: Timing Of Reset Input By Reset Input
Figure 24-2. Timing of Reset Input by RESET Input Normal Operation RESET Internal Reset Signal Port Pin Figure 24-3. Timing of Reset due to Watchdog Timer Overflow Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin Figure 24-4. Timing of Reset Input in STOP Mode by RESET Input STOP Instruction Execution Normal Operation RESET...
Page 525: Hardware Status After Reset
2. If there is a reset while in the standby mode, the status before reset is maintained even after reset is performed. 3. The values after reset depend on the product. PD78056F, 78056FY : CCH, PD78058F, 78058FY : CFH, PD78P058F, 78P058FY: CFH 4. Incorporated only in the PD78058F, 78058FY, 78P058F, and 78P058FY.
Page 526 Table 24-1. Hardware Status after Reset (2/2) Hardware Watch timer Mode control register (TMC2) Clock select register (TCL2) Watchdog timer Mode register (WDTM) Serial interface Clock select register (TCL3) Shift registers (SIO0, SIO1) Mode registers (CSIM0, CSIM1, CSIM2) Serial bus interface control register (SBIC) Slave address register (SVA) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive address pointer (ADTP)
Page 527: Chapter 25 Rom Correction
CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions The PD78058F, 78058FY Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction.
Page 528: Correction Address Registers 0 And 1 Format
(1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1.
Page 529: Rom Correction Control Registers
25.3 ROM Correction Control Registers The ROM correction is controlled with the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. The correction control register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1).
Page 530: Rom Correction Application
25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to correction address register 0, 1 (CORAD0 or CORAD1) generates the correction branch.
Page 531: Initialization Routine
CHAPTER 25 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 25-6 to correct the program. Figure 25-6. Initialization Routine ROM correction Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Note Whether the ROM correction is used or not should be judged by the port input level.
Page 532: Rom Correction Operation
CHAPTER 25 ROM CORRECTION Figure 25-7. ROM Correction Operation Internal ROM program start Does fetch address match with correction address? ROM correction Set correction status flag Correction branch (branch to address F7FDH) Correction program execution...
Page 533: Rom Correction Example
25.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 25-8. ROM Correction Example Internal ROM 0000H 0080H Program start ADD A, #1 1000H MOV B, A 1002H...
Page 534: Program Execution Flow
25.6 Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used. Figure 25-9. Program Transition Diagram (When One Place Is Corrected) FFFFH F7FFH F7FDH JUMP xxxxH 0000H (1) Branches to address F7FDH when fetch address matches correction address (2) Branches to correction program (3) Returns to internal ROM program Remark Area filled with diagonal lines : Internal expansion RAM...
Page 535: Program Transition Diagram (When Two Places Are Corrected)
CHAPTER 25 ROM CORRECTION Figure 25-10. Program Transition Diagram (When Two Places Are Corrected) FFFFH F7FFH BR !JUMP F7FDH Correction program 2 yyyyH Correction program 1 xxxxH Destination judge program JUMP Internal ROM Correction Place 2 Internal ROM Correction Place 1 Internal ROM 0000H (1) Branches to address F7FDH when fetch address matches correction address...
Page 536: Cautions On Rom Correction
25.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0 and CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0 and CORAD1) should be set when the correction enable flags (COREN0, COREN1) are “0”...
Page 537: Chapter 26 Pd78P058F, 78P058Fy
The PD78P058F and 78P058FY are products which have one time PROM incorporated into them, which it is only possible to write to once. The differences between PROM products ( PD78P058F and 78P058FY) and ROM products ( PD78056F, 78056FY, 78058F and 78058FY) are shown in Table 26-1. Table 26-1. Differences Between PD78P058F, 78P058FY and Mask ROM Versions...
Page 538: Memory Size Switching Register
ROM should be less than 56 Kbytes. The IMS settings to give the same memory map as mask ROM versions are shown in Table 26-2. Table 26-2. Examples of Memory Size Switching Register Settings Relevant Mask ROM Version PD78056F, 78056FY PD78058F, 78058FY CHAPTER 26 PD78P058F, 78P058FY...
Page 539: Internal Expansion Ram Size Switching Register
Pertinent Mask ROM Versions PD78056F, 78056FY PD78058F, 78058FY Remark If a program for the PD78P058F or 78P058FY which includes “MOV IXS, #0CH” is implemented with the PD78056F, or 78056FY, this instruction is ignored and causes no malfunction. CHAPTER 26 PD78P058F, 78P058FY After...
Page 540: Prom Programming
26.3 PROM Programming The PD78P058F and 78P058FY include on-chip PROM in a 60 Kbyte configuration as program memory. To write a program into the PD78P058F or 78P058FY PROM, make the device enter the PROM programming mode by setting the levels of the V paragraph (2) PROM programming mode in section 1.5 or 2.5 Pin Configuration (Top View).
Page 541 CHAPTER 26 (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.
Page 542: Prom Write Procedure
26.3.2 PROM write procedure Figure 26-3. Page Program Mode Flowchart Address = Address + 1 Pass CHAPTER 26 PD78P058F, 78P058FY Start Address = G = 6.5 V, V = 12.5 V Remark: G = Start address X = 0 N = Last address of program Latch Address = Address + 1 Latch...
Page 543: Page Program Mode Timing
CHAPTER 26 Figure 26-4. Page Program Mode Timing Page Data Latch A2 to A16 A0, A1 D0 to D7 Data Input +1.5 PD78P058F, 78P058FY Page Program Program Verify Hi-Z Data Output...
Page 544: Byte Program Mode Flowchart
CHAPTER 26 Figure 26-5. Byte Program Mode Flowchart Address = Address + 1 Pass PD78P058F, 78P058FY Start Remark: Address = G G = Start address N = Last address of program = 6.5 V, V = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Fail...
Page 545: Byte Program Mode Timing
CHAPTER 26 Figure 26-6. Byte Program Mode Timing A0 to A16 D0 to D7 Data Input +1.5 Cautions 1. Be sure to apply V before applying V 2. V must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied to the V pin may have an adverse affect on device reliability.
Page 546: Prom Read Procedure
CHAPTER 26 PD78P058F, 78P058FY 26.3.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V pin. Unused pins are handled as shown in paragraph, (2) PROM programming mode in section 1.5 or 2.5 Pin Configuration (Top View).
Page 547: Screening Of One-Time Prom Versions
26.4 Screening of One-Time PROM Versions One-time PROM versions cannot be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore, after users have written data into the PROM, screening should be implemented by user: that is, store devices at high temperature for one day as specified below, and verify their contents after the devices have returned to room temperature.
Page 548 [MEMO]...
Page 549: Chapter 27 Instruction Set
CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the PD78058F and 78058FY Subseries as list table. For details of its operation and operation code, refer to the separate document 78K/0 Series USER’S MANUAL—Instructions (U12326E).
Page 550: Legends Used In Operation List
27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.
Page 551: Description Of "Operation" Column
27.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter...
Page 552: Operation List
27.2 Operation List Instruction Mnemonic Operands Group r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] 8-bit data [DE], A transfer A, [HL] [HL], A...
Page 553 Instruction Mnemonic Operands Group rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX 16-bit MOVW AX, sfrp data sfrp, AX transfer Note 3 AX, rp Note 3 rp, AX AX, !addr16 !addr16, AX Note 3 XCHW AX, rp A, #byte saddr, #byte Note 4 A, r...
Page 554 Instruction Mnemonic Operands Group A, #byte saddr, #byte Note 3 A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte Note 3 A, r r, A A, saddr 8-bit...
Page 555 Instruction Mnemonic Operands Group A, #byte saddr, #byte Note 3 A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte Note 3 A, r r, A A, saddr 8-bit...
Page 556 Instruction Mnemonic Operands Group ADDW AX, #word 16-bit SUBW AX, #word operation CMPW AX, #word MULU Multiply/ divide DIVUW saddr Increment/ decrement saddr INCW DECW A, 1 A, 1 RORC A, 1 ROLC A, 1 Rotate ROR4 [HL] ROL4 [HL] ADJBA adjust ADJBS...
Page 557 Instruction Mnemonic Operands Group CY, saddr.bit CY, sfr.bit AND1 CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit XOR1 CY, A.bit manipu- CY, PSW. bit late CY, [HL].bit saddr.bit sfr.bit SET1 A.bit...
Page 558 Instruction Mnemonic Operands Group CALL !addr16 CALLF !addr11 CALLT [addr5] Call/return RETI RETB PUSH Stack manipu- late SP, #word MOVW SP, AX AX, SP !addr16 Uncondi- tional $addr16 branch $addr16 $addr16 Conditional branch $addr16 $addr16 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2.
Page 559 Instruction Mnemonic Operands Group saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Condi- saddr.bit, $addr16 tional branch sfr.bit, $addr16 BTCLR A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 B, $addr16 DBNZ C, $addr16 saddr.
Page 560: Instructions Listed By Addressing Type
CHAPTER 27 INSTRUCTION SET 27.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ...
Page 561 Second Operand Note #byte First Operand MOV MOV MOV MOV MOV MOV MOV MOV ADDC SUBC ADDC SUBC MOV MOV ADDC SUBC B, C MOV MOV saddr MOV MOV ADDC SUBC !addr16 MOV MOV [DE] [HL] [HL + byte] [HL + B] [HL + C] Note Except r = A...
Page 562 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word First Operand ADDW SUBW CMPW MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand...
Page 563 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction Compound instruction (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP CHAPTER 27 INSTRUCTION SET !addr16 !addr11 [addr5]...
Page 564 [MEMO]...
Page 565: Appendix A Differences Among Pd78054, 78058F, And 780058 Subseries
Serial interface channel 2 On-chip 3-wire serial I/O/UART mode External maskable interrupt PD78058F Subseries = 2.7 to 6.0 V PD78P058F : 16 Kbytes PD78056F : 48 Kbytes : 24 Kbytes PD78058F : 60 Kbytes : 32 Kbytes PD78P058F : 60 Kbytes...
Page 566 APPENDIX A. DIFFERENCES AMONG PD78054, 78058F, AND 780058 SUBSERIES Table A-1. Major Differences Among PD78054, 78058F, and 780058 Subseries (2/2) Product Name PD78054 Subseries Item Emulation probe EP-78230GC-R, EP-78054GK-R Device file DF78054 Package • 80-pin plastic QFP 14 mm, Resin thickness: 2.7 mm) •...
Page 567: Appendix B Development Tools
APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the PD78058F and 78058FY Subseries. Figure B-1 shows the configuration of the development tools.
Page 568: B-1 Development Tool Configuration
Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Language processing software • Assembler package • C compiler package • C library source file • Device file Tool for PROM writing • PG-1500 controller PROM writing environment PROM programmer Programmer adapter...
Page 569 Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A Language processing software • Assembler package • C compiler package • C library source file • Device file Tool for PROM writing PROM writing environment PROM programmer Programmer adapter Product with on-chip PROM...
Page 570: Language Processing Software
B.1 Language Processing Software RA78K/0 Assembler package CC78K/0 C compiler package DF78054 Note Device file CC78K/0-L C library source file Note DF78054 is common file that can be used with the RA78K/0, CC78K/0, SM78K0, ID78K0-NS, and ID78K0. Remark in part number differs depending on the host machine and OS used. RA78K0 CC78K0 DF78054...
Page 571: Prom Programming Tool
B.2 PROM Programming Tool B.2.1 Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller with on-chip PROM programmer PROM by manipulating from the stand-alone or host machine through connection of the separately available programmer adapter and the attached board. It can also program separate PROM ICs with a capacity from 256 Kbits to 4 Mbits.
Page 572: Debugging Tool
B.3 Debugging Tool B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS IE-78K0-NS Note In-circuit emulator IE-70000-MC-PS-B Power supply unit IE-70000-98-IF-C Note Interface adapter IE-70000-CD-IF Note PC card Interface Note IE-70000-PC-IF-C Interface adapter IE-780308-NS-EM1 Note Emulation board NP-80GC Emulation probe EV-9200GC-80 Conversion socket (Refer to Figure B-2)
Page 573 B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A IE-78001-R-A Note 1 In-circuit emulator IE-70000-98-IF-B or IE-70000-98-IF-C Note 1 Interface adapter IE-70000-PC-IF-B or Note 1 IE-70000-PC-IF-C Interface adapter IE-78000-R-SV3 Interface adapter IE-780308-NS-EM1 Note 1 Emulation board IE-78K0-R-EX1 Note 1 Emulation probe conversion board IE-78064-R-EM Note 2...
Page 574: Software
B.3.2 Software (1/2) SM78K0 This simulator can debug target system at C source level or assembler level while System simulator simulating operation of target system on host machine. SM78K0 runs on Windows. By using SM78K0, logic and performance of application can be verified without in-circuit emulator independently of hardware development, so that development efficiency and software quality can be improved.
Page 575 B.3.2 Software (2/2) Note ID78K0-NS Integrated debugger (Supports the in-circuit emulator IE-78K0-NS) ID78K0 Integrated debugger (Supports the in-circuit emulator IE-78001-R-A) Note Under development Remark in the part number differs depending on the host machine and OS used. ID78K0-NS AA13 PC-9800 Series AB13 IBM PC/AT and compatibles...
Page 576: Os For Ibm Pc
Table B-2. Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A In-circuit Emulator IE-78000-R IE-78000-R-A Note To upgrade your cabinet, bring it to NEC. APPENDIX B DEVELOPMENT TOOLS Table B-1. OS for IBM PC Version Ver. 5.02 to Ver. 6.3...
Page 577: B-2 Ev-9200Gc-80 Drawings (For Reference Only)
Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawings (For Reference Only) Based on EV-9200GC-80 (1) Package drawing (in mm) EV-9200GC-80 No.1 pin index APPENDIX B DEVELOPMENT TOOLS ITEM MILLIMETERS 18.0 14.4 14.4 18.0 4-C 2.0 16.0 18.7 16.0 18.7 0.35...
Page 578: B-3 Ev-9200Gc-80 Footprints (For Reference Only)
Figure B-3. EV-9200GC-80 Footprints (For Reference Only) Based on EV-9200GC-80 (2) Pad drawing (in mm) ITEM Caution APPENDIX B DEVELOPMENT TOOLS MILLIMETERS 19.7 15.0 0.65 ± 0.02 19=12.35 ± 0.05 0.026 0.65 ± 0.02 19=12.35 ± 0.05 0.026 15.0 19.7 6.0 ±...
Page 579: B-4 Tgk-080Sdw Drawings (For Reference) (Unit: Mm)
Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawings (For Reference) (unit: mm) Reference diagram: TGK-080SDW Package dimension (unit: mm) I J J J Protrusion : 4 places Note Product of TOKYO ELETECH CORPORATION. APPENDIX B DEVELOPMENT TOOLS M2 screw L L LM ITEM MILLIMETERS...
Page 580 [MEMO]...
Page 581: Appendix C Embedded Software
APPENDIX C EMBEDDED SOFTWARE This chapter describes the embedded software that is available for the PD78058F and 78058FY Subseries to allow users to develop and maintain application programs for these subseries.
Page 582: Real-Time Os
C.1 Real-time OS (1/2) RX78K/0 RX78K/0 is real-time OS conforming to ITRON specifications. Real-time OS Tool (configurator) that generates nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0) and device file (DF78054). <Precautions when using RX78K/0 under PC environment>...
Page 583 Real-time OS (2/2) MX78K0 ITRON-specification subset OS. Nucleus of MX78K0 is supplied. This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. <Precautions when using MX78K0 under PC environment> MX78K0 is a DOS-based application.
Page 584 [MEMO]...
Page 585: Appendix D Register Index
APPENDIX D REGISTER INDEX D.1 Register Index (Register Name) A/D conversion result register (ADCR) ... 264 A/D converter input select register (ADIS) ... 267 A/D converter mode register (ADM) ... 265 Asynchronous serial interface mode register (ASIM) ... 439, 447, 449, 462 Asynchronous serial interface status register (ASIS) ...
Page 586 APPENDIX D REGISTER INDEX Interrupt request flag register 1L (IF1L) ... 483, 503 Interrupt timing specify register (SINT) ... 298, 316, 351, 360, 370 Key return mode register (KRM) ... 151, 504 Memory expansion mode register (MM) ... 150, 508 Memory size switching register (IMS) ...
Page 587 Sampling clock select register (SCS) ... 186, 488 Serial bus interface control register (SBIC) ... 296, 302, 314, 333, 349, 355, 360, 369 Serial I/O shift register 0 (SIO0) ...290, 342 Serial I/O shift register 1 (SIO1) ... 390 Serial operating mode register 0 (CSIM0) ... 294, 300, 312, 331, 347, 354, 359, 368 Serial operating mode register 1 (CSIM1) ...
Page 588 CR00: Capture/compare register 00 ... 177 CR01: Capture/compare register 01 ... 177 CR10: Compare registers 10 ... 219 CR20: Compare registers 20 ... 219 CRC0: Capture/compare control register 0 ... 182 CSIM0: Serial operating mode register 0 ... 294, 300, 312, 331, 347, 354, 359, 368 CSIM1: Serial operating mode register 1 ...
Page 589 PCC: Processor clock control register ... 157 PM0: Port mode register 0 ... 130, 146 PM12: Port mode register 12 ... 130, 146, 474 PM13: Port mode register 13 ... 130, 146 PM1: Port mode register 1 ... 130, 146 PM2: Port mode register 2 ...
Page 590 TOC1: 8-bit timer output control register ... 223 TXS: Transmit shift register ... 437 WDTM: Watchdog timer mode register ... 250 APPENDIX D REGISTER INDEX...
Page 591: Appendix E Revision History
APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major Revisions from Previous Edition The following products have already been developed: PD78056GC- -8BT, 78058FGC- 78056FYGC- -8BT, 78058FYGC- The block diagrams of the following ports were changed. Figures 6-5 and 6-7 P20, P21, P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block Diagram, Figure 6-9 P30 to P37 Block Diagram, Figure 6-16 P71 and P72 Block Diagram...
Page 592 [MEMO]...
Page 593 NEC Electronics Taiwan Ltd. Fax: 02-719-5951 Excellent Good Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.

This manual is also suitable for:

Pd78056fy Pd78058fy(a)Pd78058f Pd78058f(a)Pd78058fy Pd78p058f ... Show all

NEC PD78056F User Manual

Chapter 1 Outline ( Pd78058F Subseries)

Features

Applications

Ordering Information

Quality Grade

Pin Configuration (Top View)

Series Expansion

Block Diagram

Outline of Function

Differences between the PD78058F and PD78058F(A)

Mask Options

Chapter 2 Outline ( Pd78058Fy Subseries)

Features

Applications

Ordering Information

Quality Grade

Pin Configuration (Top View)

Series Expansion

Block Diagram

Outline of Function

Differences between the PD78058FY and PD78058FY(A)

Mask Options

Chapter 3 Pin Function ( Pd78058F Subseries)

Pin Function List

Description of Pin Functions

Input/Output Circuits and Recommended Connection of Unused Pins

Chapter 4 Pin Function ( Pd78058Fy Subseries)

Pin Function List

Description of Pin Functions

Input/Output Circuits and Recommended Connection of Unused Pins

Chapter 5 Cpu Architecture

Memory Spaces

Processor Registers

Instruction Address Addressing

Operand Address Addressing

Chapter 6 Port Functions

Port Configuration

Port Function Control Registers

Port Function Operations

Selection of Mask Option

Chapter 7 Clock Generator

Clock Generator Functions

Clock Generator Configuration

Clock Generator Control Register

System Clock Oscillator

Clock Generator Operations

Changing System Clock and CPU Clock Settings

Chapter 8 16-Bit Timer/Event Counter

Overview of the PD78058F and 78058FY Subseries On-Chip Timers

16-Bit Timer/Event Counter Functions

16-Bit Timer/Event Counter Configuration

16-Bit Timer/Event Counter Control Registers

16-Bit Timer/Event Counter Operations

16-Bit Timer/Event Counter Operating Precautions

Chapter 9 8-Bit Timer/Event Counters

8-Bit Timer/Event Counter Function

8-Bit Timer/Event Counter Configuration

8-Bit Timer/Event Counter Control Registers

8-Bit Timer/Event Counter Operation

Cautions on 8-Bit Timer/Event Counters

Chapter 10 Watch Timer

Watch Timer Functions

Watch Timer Configuration

Watch Timer Control Registers

Watch Timer Operations

Chapter 11 Watchdog Timer

Watchdog Timer Functions

Watchdog Timer Configuration

Watchdog Timer Control Registers

Watchdog Timer Operations

Quick Links

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Summary of Contents for NEC PD78056F