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Address
Operation auxiliary
DT90014
register for data shift
instruction
DT90015
Operation auxiliary
register for division
instruction
DT90016
Operation error
DT90017
address (hold type)
Operation error
DT90018
address (latest type)
2.5 ms ring counter
DT90019
Note1)
10 μs ring counter
DT90020
Note1) Note2)
DT90021
Not used
Note1) It is renewed once at the beginning of each one scan.
Note2) As DT90020 is renewed even if F0(MV), DT90020 and D instruction is being executed, it can be
used to measure the block time.
5-60
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Name
One shift-out hexadecimal digit is stored in bit
positions 0 to 3 when the data shift instruction,
F105 (BSR) or F106 (BSL) is executed. The
value can be read and written by executing F0
(MV) instruction.
The divided remainder (16-bit) is stored in
DT90015 when the division instruction F32(%)
or F52(B%) instruction is executed. The
divided remainder (32-bit) is stored in
DT90015 and DT90016 when the division
instruction F33(D%) or F53(DB%) is
executed. The value can be read and written
by executing F0(MV) instruction.
After commencing operation, the address
where the first operation error occurred is
stored. Monitor the address using decimal
display.
The address where an operation error
occurred is stored. Each time an error occurs,
the new address overwrites the previous
address.
The data stored here is increased by one
every 2.5 ms. (H0 to HFFFF)
Difference between the values of the two
points (absolute value) x 2.5 ms = Elapsed
time between the two points.
The data stored here is increased by one
every 10.67 μs. (H0 to HFFFF)
Difference between the values of the two
points (absolute value) x 10.67 μs = Elapsed
time between the two points.
Note) The exact value is 10.67 μs.
-
FP0R (A: Available, N/A: Not available)
Description
Read-
Writ-
ing
ing
A
A
A
A
A
A
A
N/A
A
N/A
A
N/A
A
N/A
N/A
N/A
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