Panasonic FP-E Programming Manual page 701

FP0/FPΣ/FP−X/FP0R
F0
(MV)
Outline This instruction is used to perform control such as software reset,
counter disabling, and high−speed counter instruction clearing.
Program example
Trigger
R0
10
DF
F0 MV , H 1, DT9052 or DT90052
1
F0 MV , H 0, DT9052 or DT90052
* The high−speed counter and pulse output controls flag area
varies dependingon the PLC type.
S
Operands
Relay
Operand Operand
WX WY WR
S A A
(*1) I0 to IC on FPΣ/FP−X/FP0R
(*2) ID on FPΣ/FP−X/FP0R
Description
Performs high−speed counter control according to the control code specified in "S".
This instruction is used to perform the following operations when using a high−speed counter:
<Function>
1) Performing a software reset
2) Disabling the count
3) Temporarily disables reset input setting using external inputs
4) Clearing control executed with high−speed counter and pulse output instructions F166 or F167.
Once written, a control code is retained until the next write operation.
Precautions during programming
Hardware resets can only be disabled if a reset input is used.
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High−speed counter control
Ladder Diagram Ladder Diagram
High speed counter
S
Pulse output
Controls flag
Area for storing high−speed counter control code or constant data
Timer/Counter Register
SV EV DT
A A A A
1
and
area
Index
Constant
register
modifier
IX IY
K H
(*1) (*2)
A A A A
High−level Instructions
Availability
FP0/FP0R/FPΣ/FP−X
Boolean
Address Instruction
10 ST R
11 DF
12 F0 (MV)
H
DT 9052
17 F0 (MV)
H
DT 9052
Index Index
A A: Available
3 − 437
0
1
0