Panasonic FP-E Programming Manual page 1265

FP2/FP2SH/FP3/FP10SH (A: Available, N/A: Not available)
Address
FP2/
FP3 FP2SH
FP10SH
DT9006 DT90006
DT9007 DT90007
DT9010 DT90010
DT9011 DT90011
DT9014 DT90014
DT9015 DT90015
DT9016 DT90016
DT9017 DT90017
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Name
When an error condition is detected in
an intelligent unit, the bit corresponding
Abnormal
to the slot of the unit will be set to on.
intelligent unit
Monitor using binary display.
(slot No. 0 to 15)
(1: abnormal intelligent unit, 0: normal
intelligent unit)
Abnormal
intelligent unit
(slot No. 16 to
31)
When the state of installation of an I/O
unit has changed since the power was
I/O verify error
turned on, the bit corresponding to the
unit (slot No. 0
slot of the unit will be set to on. Monitor
to 15)
using binary display.
(1: error, 0: normal)
I/O verify error
unit (slot No. 16
to 31)
One shift-out hexadecimal digit is stored
Auxiliary
in bit positions 0 to 3 when F105
register for
(BSR)/P105 (PBSR) or f106 (BSL)/P106
operation
(PBSL) instruction is executed.
The divided remainder (16-bit) is stored
in DT9015/DT90015 when F32 (%)/P32
(P%) or F52(B%)/P52 (PB%) instruction
Auxiliary
is executed.
register for
The divided remainder (32-bit) is stored
operation
in DT9015 and DT9016/DT90015 and
DT90016 when F33 (D%)/P33 (PD%) or
F53(DB%)/P53 (PDB%) instruction is
executed.
After commencing operation, the
address whre the first operation error
Operation error
occurred is stored. Monitor the address
address (hold)
using decimal display.
(Reference: DT90257)
Descriptions
Read- Writ-
ing ing
A N/A
5-177