ARM ARM966E-S Technical Reference Manual page 46

Tightly-coupled SRAM
4-10
FOURSEGX8
Figure 4-5 on page 4-11 shows that the SRAM needs to be split into four-byte wide
segments where an SRAM does not support byte-writes. In order to give an example of
the most complex interface possible, Figure 4-5 on page 4-11 assumes that each
byte-wide SRAM needs to be split into four blocks (see word-wide SRAM in
FOURSEGX32 on page 4-9).
In FOURSEGX32 on page 4-9 the SRAM Address is 11 bits. Bits [12:11] of the address
are used to decode which of the four word-wide RAMs is selected.
In Figure 4-5 on page 4-11 ByteWrite[3:0] is used (inside IRamIF.v) to decode each
word-wide chip select into four separate chip select signals, one for each byte of the
word.
Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A