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Test Support
10.1
About the ARM966E-S test methodology
10-2
To achieve a high level of fault coverage, scan insertion and ATPG techniques are used
on the ARM9E-S core and ARM966E-S control logic as part of the synthesis flow.
BIST is used to provide high fault coverage of the compiled SRAM.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0186A
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