Figure 6-6 Single Stm, No Instruction Fetch; Stm Timing; Ldm Timing - ARM ARM966E-S Technical Reference Manual

ARM DDI 0186A

STM timing

Figure 6-6 shows the timing for an
the AHB are not driven during IDLE cycles, and so hold their previous value. This
includes the HBURST output, continuing to indicate INCRemental until the next
nonsequential transfer. This should not cause any confusion to other AHB components
as HTRANS indicates IDLE cycles.
CLK
HBUSREQ
HGRANT
NONSEQ
HTRANS
HBURST
HADDR
HWRITE
HWDATA
HREADY
Note
If an is not immediately followed by an external instruction access one IDLE cycle
STM
is inserted, and HBUSREQ is driven LOW. An
AHB data access, also results in one IDLE cycle being inserted between the two
accesses.

LDM timing

Figure 6-7 on page 6-12 shows the timing for an
words.
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instruction, transferring three words. Outputs to
STM
SEQ SEQ
DA-1 DA-2
DD-1 DD-2

Figure 6-6 Single STM, no instruction fetch

STM
Bus Interface Unit
IDLE
001
DA-3
DD-3
, immediately followed by any other
LDM instruction, transferring three
6-11