Simultaneous Instruction Fetch, Data Read - ARM ARM966E-S Technical Reference Manual

C.1.2 Additional Instruction SRAM stalls
ARM DDI 0186A
Figure C-2 shows this example and how the SRAM control must pipeline and select
between the write and read address. The ARM9E-S core is stalled for a cycle by the
system controller by deasserting SYSCLKEN.
CLK
DnMREQ
DnRW
DA[31:1]
SRAM Addr
WDATA[31:0]
RDATA[31:0]
SYSCLKEN
Note
The second rising edge of the SRAM write cycle is the same edge that is required for
the SRAM read (of Addr B). It is not possible to read and write concurrently so a stall
must occur before the read of Addr B.
The I-SRAM has additional stall cycles that arise because of the following operations:
• data reads to the I-SRAM are pipeline
• simultaneous instruction fetches and data accesses can occur
• any access can occur during two cycle data reads and writes.

Simultaneous instruction fetch, data read

The ARM9E-S data interface is able to access the I-SRAM for programming purposes
and for access to literal tables during program execution.
Copyright © 2000 ARM Limited. All rights reserved.
SRAM write
cycle
Addr A (write) Addr B (read)
Addr A
Write data (A)
Figure C-2 Read follows write
SRAM Stall Cycles
stall SRAM read
cycle cycle
Addr B
Read data (B)
C-3