Ahb Signals; Table A-2 Ahb Signals; A.3 Ahb Signals - ARM ARM966E-S Technical Reference Manual

Signal Descriptions
A.3

AHB signals

A-4
Table A-2 describes the ARM966E-S AHB signals.
Name Direction
HADDR[31:0] Output
Address bus
HTRANS[1:0] Output
Transfer type
HWRITE Output
Transfer direction
HSIZE[2:0] Output
Transfer size
HBURST[2:0] Output
Burst type
HPROT[3:0] Output
Protection control
HWDATA[31:0] Output
Write data bus
HRDATA[31:0] Input
Read data bus
HREADY Input
Transfer done
HRESP[1:0] Input
Transfer response
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Description
The 32-bit AHB system address bus.
Indicates the type of ARM966E-S transfer, which
can be IDLE (00), NONSEQ (10), or SEQ (11).
When HIGH indicates a write transfer. When LOW
indicates a read transfer.
Indicates the size of an ARM966E-S transfer, which
can be Byte (000), Half-word (001) or Word (010).
Indicates if the transfer forms part of a burst. The
ARM966E-S supports SINGLE transfer (000) and
INCRemental burst of unspecified length (001).
Indicates that the ARM966E-S transfer is an opcode
fetch (0--0) or a data access (0--1) or a User mode
access (0-0-) or a Supervisor mode access (0-1-).
Also indicates that an access is not bufferable (00--)
or bufferable (01--). Bit [3] is driven to 0 indicating
not cacheable.
The 32-bit write data bus is used to transfer data from
the ARM966E-S to a selected bus slave during write
operations.
The 32-bit read data bus is used to transfer data from
a selected bus slave to the ARM966E-S during read
operations.
When HIGH indicates that a transfer has finished on
the bus. This signal can be driven LOW by the
selected bus slave to extend a transfer.
The transfer response from the selected slave
provides additional information on the status of the
transfer. The response can be OKAY (00), ERROR
(01), RETRY (10), or SPLIT (11).

Table A-2 AHB signals

ARM DDI 0186A