Simultaneous Instruction Fetch, Data Write - ARM ARM966E-S Technical Reference Manual

SRAM Stall Cycles
C-6
RDATA[31:0]

Simultaneous instruction fetch, data write

If the ARM9E-S performs a simultaneous data write and instruction fetch that both map
to I-SRAM address space, two stall cycles occur. The first cycle allows for the pipelined
write, the second cycle allows for the instruction fetch. The core cannot be enabled until
both accesses have completed (see Figure C-6 on page C-7).
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CLK
DnMREQ
InMREQ
DnRW
DA[31:0] Addr A(read)
IA[31:0]
I-SRAM
Addr
INSTR[31:0]
SYSCLKEN
Figure C-5 Data read followed by instruction fetch
stall data instr
cycle read fetch
Addr B(fetch)
Addr A Addr B
Read data (A)
Read data (B)
ARM DDI 0186A