Figure 4-4 Foursegx32 Interface - ARM ARM966E-S Technical Reference Manual

ARM DDI 0186A
FOURSEGX32
You can use the example shown in Figure 4-4 when it is not possible to construct the
SRAM from a single physical block due to either layout constraints or generator
constraints, or because a single SRAM segment does not meet timing constraints.
ByteWrite[3:0]
ICtrl.v
RamAddr[10:0]
WriteEnable
ChipSelect[3:0]
IRamIF.v
OutputSelect[1:0]
Separate chip select signals are required for each SRAM block.
Note
• The generation of separate chip select signals for each SRAM block ensures good
power performance, because only the segment being accessed is enabled.
• The SRAM address is 11 bits in this example (compared with the 13 bit address
in ONESEGX32 on page 4-8). RamAddr[12:11] are used to generate separate
chip selects for each segment.
If it is not possible to have separate chip select signals for each block of RAM, for
example if the RAM is asynchronous, then separate write enable signals are required
for each segment. The use of asynchronous RAMs is not recommended due to the
increased power consumption of this solution.
Note
The wrapper RTL does not support asynchronous RAMs.
Copyright © 2000 ARM Limited. All rights reserved.
2Kx32 2Kx32
[0] [1]
[31:0] [63:32]

Figure 4-4 FOURSEGX32 interface

Tightly-coupled SRAM
2Kx32 2Kx32
[2] [3]
[95:64] [127:96]
IRData[31:0]
4-9