Figure 5-6 Dual-Port Ram Dma Writes - ARM ARM966E-S Technical Reference Manual

5.2.5 Mixed read and writes
ARM DDI 0186A
DMAReady is redundant for dual-port RAM accesses and does not need to be sampled
by the DMA controller.
DMAENABLE must be asserted one cycle prior to a request being made and can be
deasserted when DMAnREQ is taken HIGH after the last request.
CLK
DMAENABLE
DMAnREQ
DMAWait
DMAnRW
DMAReady
DMAAddr
DMAWData
Figure 5-7 on page 5-10 shows:
• an example of intermingled DMA read and write operations
• that reads and writes can be performed back-to-back.
The behavior is the same for both single and dual-port RAMs. Depending on whether
the RAM was single or dual-port, the behavior of DMAENABLE, DMAWait, and
DMAReady is described in sections Single-port RAM reads on page 5-5 to Dual-port
RAM writes on page 5-8.
Copyright © 2000 ARM Limited. All rights reserved.
Direct Memory Access (DMA)
Write1 Write2
A1 A2
D1 D2

Figure 5-6 Dual-port RAM DMA writes

5-9