ARM ARM966E-S Technical Reference Manual page 9

List of Figures
ARM966E-S Technical Reference Manual
Figure 1-1
Figure 3-1
Figure 3-2
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
ARM DDI 0186A
Key to timing diagram conventions ............................................................................ xiv
ARM966E-S block diagram ....................................................................................... 1-3
ARM966E-S memory map ........................................................................................ 3-2
I-SRAM aliasing example .......................................................................................... 3-3
SRAM read cycle ...................................................................................................... 4-2
ARM966E-S SRAM hierarchy ................................................................................... 4-7
ONESEGX32 interface .............................................................................................. 4-8
FOURSEGX32 interface ........................................................................................... 4-9
FOURSEGX8 interface ........................................................................................... 4-11
Single-port RAM DMA interface ................................................................................ 5-3
Dual-port RAM DMA interface ................................................................................... 5-4
Single-port RAM DMA reads ..................................................................................... 5-5
Single-port RAM DMA writes .................................................................................... 5-7
Dual-port DMA reads ................................................................................................ 5-8
Dual-port RAM DMA writes ....................................................................................... 5-9
Mixed DMA read and write ...................................................................................... 5-10
Write buffer FIFO content example ........................................................................... 6-4
Sequential instruction fetches, after being granted the bus ...................................... 6-8
Sequential instruction fetches, no AHB data access required .................................. 6-9
Back-to-back LDR, no external instruction access .................................................... 6-9
Simultaneous instruction and data requests ........................................................... 6-10
Single STM, no instruction fetch ............................................................................. 6-11
Single LDM, no instruction access .......................................................................... 6-12
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