Timing Interface; Figure 5-3 Single-Port Ram Dma Reads - ARM ARM966E-S Technical Reference Manual

5.2

Timing interface

5.2.1 Single-port RAM reads
DMAENABLE
DMAnREQ
DMAWait
DMAnRW
DMAReady
DMAAddr
DMARData
ARM DDI 0186A
To ease the system integration task and to provide RAM independent timings, the
ARM966E-S registers all DMA inputs and outputs. This section details the behavior of
the ARM966E-S for DMA read and writes to single and dual-port RAMs.
Note
The dual-port RAM DMA solution also supports the single-port operation and so the
single-port diagrams are also applicable to dual-port RAMs.
Figure 5-3 shows DMA read operation from a single-port RAM.
DMA read request
CLK
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Read latency
Core Stalled
A1 A2

Figure 5-3 Single-port RAM DMA reads

Direct Memory Access (DMA)
D1 D2
5-5