Figure 5-4 Single-Port Ram Dma Writes - ARM ARM966E-S Technical Reference Manual

5.2.3 Dual-port RAM reads
ARM DDI 0186A
The behavior of DMAWait is as for single-port RAM reads.
DMAENABLE must be asserted one cycle prior to a request being made and can be
deasserted when DMAnREQ is taken HIGH after the last request.
CLK
DMAENABLE
DMAnREQ
DMAWait
DMAnRW
DMAReady
DMAAddr
DMAWData
Figure 5-5 on page 5-8 shows DMA read operations to a dual-port RAM.
A read request is initiated by taking DMAnREQ and DMAnRW both LOW. The
address, DMAAddr, must be valid in the same cycle. The read data, DMARData, is
returned in the third cycle after the request is registered by the ARM966E-S (one cycle
to register the request, one cycle to read the RAM, and one cycle to register the output
data).
Note
Because the ARM966E-S core does not need to be stalled for dual-port DMA accesses,
the DMA controller can access the data RAM continuously. DMAWait must be tied
LOW otherwise the DMA access is by the first port of the RAM and the interface
behaves as described in Single-port RAM reads on page 5-5.
DMAReady is redundant for dual-port RAM accesses and does not need to be sampled
by the DMA controller.
Copyright © 2000 ARM Limited. All rights reserved.
Direct Memory Access (DMA)
Write1 Write2
A1 A2
D1
D2

Figure 5-4 Single-port RAM DMA writes

5-7