ARM ARM966E-S Technical Reference Manual page 26

Programmer's Model
2-6
Bit 15, Configure disable loading TBIT
When HIGH the ARM9E-S core disables certain ARMv5T defined behavior involving
loading data to the PC. This bit is cleared LOW during reset to provide ARMv5T
compatibility.
Bit 13, Alternate vectors select
This bit controls the base address used for the exception vectors. When LOW, the base
address for the exception vectors is
.
0xFFFF 0000
Note
Bit 13 is initialized either HIGH or LOW during system reset, depending on the value
of the input pin, VINITHI. This allows the exception vector location to be defined
during reset to suit the boot mechanism of the application. You can then reprogram as
required following system reset.
Bit 12, Instruction SRAM enable
This bit controls the behavior of the tightly-coupled instruction SRAM. When HIGH,
all accesses to the fixed instruction memory space as shown in Figure 3-1 on page 3-2,
access the instruction SRAM. When LOW, all accesses to the instruction memory space
access the AMBA AHB.
Copyright © 2000 ARM Limited. All rights reserved.
Table 2-3 Register 1, Control register (continued)
Register
bit
11:8
7
6:4
3
2
1:0
. When HIGH, the base address is
0x0000 0000
Function
Reserved (should be one)
Endian
Reserved (should be one)
Write buffer enable
Data SRAM enable
Reserved (should be zero)
ARM DDI 0186A