ARM ARM966E-S Technical Reference Manual page 28

Programmer's Model
2-8
Wait for interrupt
This operation allows the ARM966E-S to enter a low-power standby mode. When the
operation is invoked, the clock enable to the processor core is negated until either an
interrupt or a debug request occurs. This function is invoked by a write to Register 7.
The following ARM instruction causes this to occur:
MCR p15, 0, rd, c7, c0, 4; wait for interrupt
This is the preferred encoding that must be used by new software. For compatibility
with existing software, ARM966E-S also supports the following ARM instruction that
has the same affect:
MCR p15, 0, rd, c15, c8, 2; wait for interrupt
This stalls the processor from the time that the instruction is executed until nFIQ,
nIRQ, or EDBGRQ are asserted. Also, if the debugger sets the debug request bit in the
EmbeddedICE-RT control register then this causes the wait-for-interrupt condition to
terminate.
In the case of nFIQ and nIRQ, the processor core is woken up regardless of whether
the interrupts are enabled or disabled (that is, independent of the I and F bits in the
processor CPSR). The debug-related waking only occurs if DBGEN is HIGH, that is,
only when debug is enabled.
If interrupts are enabled, the ARM9E-S core is guaranteed to take the interrupt before
executing the instruction after the wait for interrupt. If debug request is used to wake up
the system, the processor enters debug-state before executing any more instructions.
Wait for interrupt does not prevent the write buffer from emptying.
Drain write buffer
This CP15 operation causes instruction execution to be stalled until the write buffer is
emptied. This operation is useful in real-time applications where the processor has to be
sure that a write to a peripheral has completed before program execution continues. An
example is where a peripheral in a bufferable region is the source of an interrupt. When
the interrupt has been serviced, the request must be removed before interrupts can be
re-enabled. This can be ensured if a drain write buffer operation separates the store to
the peripheral and the enable interrupt functions.
The drain write buffer operation is invoked by a write to Register 7 using the following
ARM instruction:
MCR cp15, 0, rd, c7, c10, 4; drain write buffer
Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A