ARM ARM966E-S Technical Reference Manual page 42

Tightly-coupled SRAM
4-6
Disabling the D-SRAM
You can disable the D-SRAM by clearing bit 2 of the CP15 control register. When the
D-SRAM is disabled, all further reads and writes to the D-SRAM address space, as
shown in Figure 3-1 on page 3-2, access the AHB. Read and write accesses to I-SRAM
address space uses the I-SRAM or accesses the AHB depending on if it is enabled.
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