Busy-Waiting And Interrupts; Figure 7-6 Busy-Waiting And Interrupts - ARM ARM966E-S Technical Reference Manual

Coprocessor Interface
7.7

Busy-waiting and interrupts

Coprocessor
pipeline
CLK
CPINSTR[31:0]
nCPMREQ
CPPASS
CPLATECANCEL
CHSDE[1:0]
CHSEX[1:0]
7-12
The coprocessor is permitted to stall, or busy-wait, the processor during the execution
of a coprocessor instruction if, for example, it is still busy with an earlier coprocessor
instruction. To do so, the coprocessor associated with the Decode stage instruction
drives WAIT onto CHSDE[1:0]. When the instruction concerned enters the Execute
stage of the pipeline, the coprocessor drives WAIT onto CHSEX[1:0] for as many
cycles as necessary to keep the instruction in the busy-wait loop.
For interrupt latency reasons the coprocessor might be interrupted while busy-waiting,
causing the instruction to be abandoned. Abandoning execution is done through
CPPASS. The coprocessor must monitor the state of CPPASS during every busy-wait
cycle.
If it is HIGH, the instruction must still be executed. If it is LOW, the instruction must
be abandoned.
Figure 7-6 shows a busy-waited coprocessor instruction being abandoned due to an
interrupt.
Fetch
INSTR
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Decode
Execute Execute
(WAIT) (WAIT)
WAIT
WAIT WAIT

Figure 7-6 Busy-waiting and interrupts

Abandoned
Execute Execute
(WAIT) (WAIT)
WAIT Ignored
ARM DDI 0186A