ARM ARM966E-S Technical Reference Manual page 27

2.3.4 Register 7, Core control
ARM DDI 0186A
Note
Bit 12 is initialized either HIGH or LOW during system reset depending on the value of
the input pin INITRAM.
Bit 7, Endian
Selects the endian configuration of the ARM966E-S. When this bit is HIGH, big-endian
configuration is selected. When LOW, little-endian configuration is selected. This bit is
cleared LOW during reset.
Bit 3, Write buffer enable
This bit controls the use of the write buffer. When HIGH, all stores to the fixed
bufferable space of the AMBA AHB (as shown in Figure 3-1 on page 3-2) are treated
as buffered writes. When LOW, all stores to the AMBA AHB are treated as
nonbufferable.
If the write buffer is disabled having previously been enabled, any writes already in the
write buffer FIFO complete as buffered writes.
This bit is cleared LOW during reset.
Bit 2, Data SRAM enable
This bit controls the behavior of the tightly-coupled Data SRAM. When HIGH, all data
interface accesses to the fixed data memory space as shown in Figure 3-1 on page 3-2,
access the Data SRAM. When LOW, all accesses to the data memory space access the
AMBA AHB.
Note
Bit 2 is initialized either HIGH or LOW during system reset depending on the value of
the input pin INITRAM.
You can use a write to this register, to perform wait for interrupt and drain write buffer
operations.
Copyright © 2000 ARM Limited. All rights reserved.
Programmer's Model
2-7