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10.3.2
BIST address and general registers
ARM DDI 0186A
Note
Clearing the functional SRAM enable when BIST is enabled prevents the programmer
from trying to run from tightly coupled SRAM following a BIST test, without having
first reprogrammed the SRAM. This is necessary as the BIST algorithm corrupts all
tested SRAM locations.
The BIST control register enables standard BIST operations to be performed on each
SRAM and the size of the test to be specified. Additional registers are required however,
to provide the following functionality:
•
testing of the BIST hardware
•
changing the seed data for a BIST test
•
providing a nonzero starting address for a BIST test
•
peek and poke of the SRAM
•
returning an address location for a failed BIST test
•
returning failed data from the failing address location.
This additional functionality is most useful for debugging faulty silicon during
production test. The exception to this is the start address for a BIST test. It is possible
that BIST of the SRAM is performed periodically during program execution, the
memory being tested in smaller pieces rather than in one go. This requires a start
address that is incremented by the size of the test each time a test is activated.
Table 10-1 and Table 10-2 on page 10-6 show how the registers are used. The pause bits
from the BIST control register provide extra decode of these registers.
BIST register
IBIST address register
IBIST address register
IBIST general register
IBIST general register
Copyright © 2000 ARM Limited. All rights reserved.
Table 10-1 Instruction BIST address and general registers
IBIST
Read
pause
0
IBIST fail address
1
IBIST fail address
0
IBIST fail data
1
IBIST peek data
Test Support
Write
IBIST start address
IBIST peek/poke address
IBIST seed data
IBIST poke data
10-5
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