Interlocked Mcr; Figure 7-3 Interlocked Mcr/Mrc Timing With Busy-Wait - ARM ARM966E-S Technical Reference Manual

7.4

Interlocked MCR

Coprocessor
pipeline
CLK
CPINSTR[31:0]
nCPMREQ
CPPASS
CPLATECANCEL
CHSDE[1:0]
CHSEX[1:0]
CPDIN[31:0]
MRC
CPDOUT[31:0]
MCR
ARM DDI 0186A
If the data for a operation is not available inside the ARM9E-S core pipeline during
MCR
its first Decode cycle, then the ARM9E-S core pipeline interlocks for one or more
cycles until the data is available. An example of this is where the register being
transferred is the destination from a preceding
In this situation the
MCR
and then remains there for a number of cycles before entering the Execute stage.
Figure 7-3 gives an example of an interlocked
Fetch
MCR/MRC
Copyright © 2000 ARM Limited. All rights reserved.
instruction enters the Decode stage of the coprocessor pipeline,
Decode
Decode Execute
(interlock) (WAIT)
WAIT WAIT
LAST

Figure 7-3 Interlocked MCR/MRC timing with busy-wait

Coprocessor Interface
instruction.
LDR
that also has a busy-wait state.
MCR
Memory
Execute
(LAST)
Ignored
Coproc to ARM
Write
ARM to coproc
7-9