Tightly-Coupled Sram Cycles; Table 11-1 I-Sram Access - ARM ARM966E-S Technical Reference Manual

Instruction cycle timings
11.3

Tightly-coupled SRAM cycles

11-4
This section describes the stall cycle counts for accesses to one or both of the SRAMs.
The circumstances where the internal tightly-coupled SRAM can stall are detailed in
SRAM stall cycles on page 4-3.
Table 11-1 lists the stall cycles incurred when accessing the I-SRAM. In most cases the
data accesses are to the D-SRAM so the stall penalties listed are not incurred.
Instruction sequence
Single instruction fetch
Sequential instruction fetch
LDR , no instruction fetch
LDR , simultaneous
instruction fetch
, instruction fetch in
LDM
parallel with final load
, no instruction fetch
STR
simultaneous
STR
instruction fetch
followed by instruction
STR
fetch
followed by
STR
simultaneous, instruction
fetch
LDR
STR followed by
simultaneous instruction
fetch, STR
followed by / , no
STR LDR STR
instruction fetch
, instruction fetch in
STM
parallel with final store
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Stalls Comment
0 Assuming no data interface access to I-SRAM
0 Assuming no data interface access to I-SRAM
0 Assuming no previous I-SRAM store
1 Simultaneous instruction fetch request causes stall
of LDR for 1 cycle
1 Simultaneous instruction fetch request at end of
causes stall
0 Assuming no previous ISRAM store
2 Two cycle write performed prior to instruction fetch
1 Stall occurs due to second cycle of store
1 Stall occurs due to second cycle of store
2 Stall due to second cycle of second store plus
instruction fetch request
1 Stall due to second cycle of store
2 Simultaneous instruction fetch request must wait for
second cycle of final write to complete

Table 11-1 I-SRAM access

LDM
ARM DDI 0186A