Monitor Mode Debug - ARM ARM966E-S Technical Reference Manual

8.10

Monitor mode debug

ARM DDI 0186A
The ARM9E-S within ARM966E-S contains logic that allows the debugging of a
system without stopping the core entirely. This allows the continued servicing of critical
interrupt routines while the core is being interrogated by the debugger. Setting bit 4 of
the debug control register enables the real-time debug features of ARM9E-S. When this
bit is set, the EmbeddedICE-RT logic is configured so that a breakpoint or watchpoint
causes the ARM to enter abort mode, taking the Prefetch Abort or Data Abort vectors
respectively. When the ARM is configured for real-time debugging you must be aware
of the following restrictions:
• Breakpoints or watchpoints might not be data dependent. No support is provided
for use of the range and chain functionality. Breakpoints or watchpoints can only
be based on:
— instruction or data addresses
— external watchpoint conditioner (DBGEXTERN)
— user or privileged mode access (DnTRANS and InTRANS)
— read or write access (watchpoints)
— access size (breakpoints, ITBIT, and watchpoints, DMAS[1:0]).
• The single-step hardware is not enabled.
• External breakpoints and watchpoints are not supported.
• The vector catching hardware can be used but must not be configured to catch the
Prefetch or Data Abort exceptions.
Caution
No support is provided to mix halt mode and monitor mode debug functionality. When
the core is configured into the monitor mode, asserting the external EDBGRQ signal
results in unpredictable behavior. Setting the internal EDBGRQ bit results in
unpredictable behavior.
When an abort is generated by the monitor mode it is recorded in the debug status
register in coprocessor 14 (see Communications channel monitor mode debug status
register on page 8-21).
Because the monitor mode debug does not put the ARM9E-S into debug state, it is
necessary to change the contents of the watchpoint registers while external memory
accesses are taking place, rather than being changed when in debug state. If the
watchpoint registers are written to during an access, all matches from the affected
watchpoint unit using the register being updated are disabled for the cycle of the update.
Copyright © 2000 ARM Limited. All rights reserved.
Debug Support
8-23