Table 11-5 Ahb Buffered Writes Cycles - ARM ARM966E-S Technical Reference Manual

AHB access
Single
STR
Back-to-back STR/STR
STM
Last in write buffer drain followed
STR
by unbuffered data access
Last in write buffer drain followed
STR
by instruction fetch
ARM DDI 0186A
Cycles
Sync+N+I
Sync+2(N+I)
Sync+N+(n-1)S+I
2(N+I)
2N+I
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Instruction cycle timings

Table 11-5 AHB buffered writes cycles

Comment
Assumes no following AHB
instruction fetch
Assumes no following AHB
instruction fetch
Assumes no following AHB
instruction fetch
Core stalled until write buffer empty
and data access has been performed
Optimization replaces IDLE cycle
after store with NONSEQ of
instruction fetch
11-9