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Chapter 11
Instruction cycle timings
ARM DDI 0186A
This chapter describes the instruction cycle timings for the ARM966E-S. It contains the
following sections:
•
Introduction to instruction cycle timings on page 11-2
•
When stall cycles do not occur on page 11-3
•
Tightly-coupled SRAM cycles on page 11-4
•
AHB memory access cycles on page 11-6
•
Interrupt latency calculation on page 11-10
Copyright © 2000 ARM Limited. All rights reserved.
11-1
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