Enabling The Sram - ARM ARM966E-S Technical Reference Manual

Tightly-coupled SRAM
4.3

Enabling the SRAM

4.3.1 Using INITRAM input pin
4-4
There are two mechanisms for controlling the enable of the SRAM:
• both I-SRAM and D-SRAM can be enabled or disabled during reset by the input
pin INITRAM
• the I-SRAM and D-SRAM can be individually enabled or disabled through
software instructions to CP15.
MCR
Two resets are described in the following sections:
• Reset with INITRAM LOW
• Reset with INITRAM HIGH.
Reset with INITRAM LOW
The INITRAM pin is provided to allow the ARM966E-S to boot with both SRAM
blocks either enabled or disabled. If INITRAM is held LOW during reset, the
ARM966E-S comes out of reset with both SRAMs disabled. All accesses to I-SRAM
and D-SRAM space go to the AHB. The SRAM can then be individually or jointly
enabled by writing to the CP15 control register (register 1).
Reset with INITRAM HIGH
If however, INITRAM is held HIGH during reset, both SRAM blocks are enabled
when the ARM966E-S comes out of reset. This is normally used for a warm reset where
the SRAM has already been programmed before the application of nRESET to the
ARM966E-S. In this case, the SRAM contents are preserved and the ARM966E-S can
run directly from the tightly-coupled SRAM following reset. Either one or both SRAM
can be further disabled or enabled by writing to the CP15 control register.
Note
If INITRAM is held HIGH during a cold reset (the SRAM has not previously been
initialized), the VINITHI pin must be set HIGH to ensure that the ARM966E-S boots
from , that is in AHB address space and is substantially outside the SRAM
0xFFFF 0000
address space. This is necessary because if VINITHI is LOW, the ARM966E-S
attempts to boot from
0x0000 0000
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, and this selects the uninitialized I-SRAM.
ARM DDI 0186A