Figure 8-3 Arm9E-S Block Diagram - ARM ARM966E-S Technical Reference Manual

8.2.3 ARM966E-S debug target
ARM DDI 0186A
The ARM9E-S core within the ARM966E-S has hardware extensions that ease
debugging at the lowest level. The debug extensions:
• allow you to stall the core from program execution
• examine the core internal state
• examine the state of the memory system
• resume program execution.
The following major blocks of the ARM9E-S debug model are shown in Figure 8-3.
ARM9E-S CPU core This includes hardware support for debug.
EmbeddedICE-RT logic This is a set of registers and comparators used to generate
debug exceptions (such as breakpoints). This unit is described in
About the EmbeddedICE-RT on page 8-16.
TAP controller This controls the action of the scan chains using a JTAG serial
interface.
Scan chain 2
The ARM9E-S debug model is extended within the ARM966E-S by the addition of
scan chain 15. This is used for debug access to the CP15 register bank, to allow the
system state within the ARM966E-S to be configured while in debug state, for instance
to enable or disable the SRAM before performing a debug load or store.
Copyright © 2000 ARM Limited. All rights reserved.
ARM9E-S
EmbeddedICE-RT
ARM9E-S
TAP controller

Figure 8-3 ARM9E-S block diagram

Debug Support
Scan chain 1
ARM9E-S
8-5