B.1 Timing Diagrams - ARM ARM966E-S Technical Reference Manual

AC Parameters
B.1 Timing diagrams
B-2
The timing diagrams in this section are:
• Clock, reset and AHB enable timing
• AHB bus request and grant related timing on page B-3
• AHB bus master timing on page B-4
• Coprocessor interface timing on page B-5
• Debug interface timing on page B-6
• JTAG interface timing on page B-7
• DBGSDOUT to DBGTDO timing on page B-8
• Exception and configuration timing on page B-8
• INTEST wrapper timing on page B-9
• ETM interface timing on page B-10.
Clock, reset and AHB enable timing parameters are shown in Figure B-1.
AHB bus request and grant related timing parameters are shown in Figure B-2 on
page B-3.
Copyright © 2000 ARM Limited. All rights reserved.
Figure B-1 Clock, reset and AHB enable timing
ARM DDI 0186A