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Instruction cycle timings
11.4
AHB memory access cycles
11.4.1
Synchronization penalty
11-6
When a read or non-bufferable write access to the AHB is performed, stall cycles are
introduced. The number of CLK stall cycles incurred depends on:
•
the clocking ratio of the AHB interface
•
the type of access being performed
•
if there are further accesses to be performed.
Before an AHB transfer can be initiated, the ARM966E-S must be the granted bus
master. The cycle calculations in this section assume that the ARM966E-S is granted
and that it is the default bus master.
At the start of an AHB access, the BIU within the ARM966E-S must wait for the first
rising edge of HCLK (the HCLKEN input is true) before it can broadcast the necessary
AHB control and address information for the access. This delay is the synchronization
penalty. The best case is that in the cycle when the AHB access is requested, the
HCLKEN input is HIGH, incurring a zero cycle synchronization penalty. The worst
case is where the HCLKEN is HIGH in the cycle before the AHB access is required.
The ARM966E-S must then wait until the next assertion of HCLKEN which is R-1
cycles later, where R is the CLK to HCLK ratio:
•
Best case synchronization penalty is 0 CLK cycles
•
Worst case synchronization penalty is R-1 CLK cycles, where R = 1, 2, 3, 4, 5, 6,
7, 8 for example.
If the AHB must be accessed for two transfers that were requested simultaneously by
the ARM9E-S core (that is, a simultaneous instruction fetch and data load), the BIU
stays synchronized after the first transfer so that the penalty is only incurred for the first
access. If the transfer is part of a burst (
sequence, again the BIU stays synchronized between each transfer to minimize
synchronization penalty.
Note
If the clock ratio R=1 and the HCLKEN input to the ARM966E-S is tied HIGH then
no synchronization penalty is incurred when accessing the AHB.
Copyright © 2000 ARM Limited. All rights reserved.
STM/LDM
) or a sequential instruction fetch
ARM DDI 0186A
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