ARM ARM966E-S Technical Reference Manual page 188

Index
DBGEN 8-18, A-9
DBGEXT A-9
DBGIEBKPR 8-18
DBGIEBKPT A-10
DBGINSTREXEC A-9
DBGIR A-8
DBGnTDOEN A-8
DBGnTRST A-8
DBGRNG A-9
DBGRQ A-9
DBGSCREG A-8
DBGSDIN A-8
DBGSDOUT A-8
DBGTAPSM A-8
DBGTCKEN 8-14, A-3
DBGTDI A-8
DBGTDO A-8
DBGTMS A-8
Debug
communcations data read register
8-19
communications channel 8-21
communications channel register
8-19
communications channel status
register 8-19
communications data write register
8-19
communicationss channel 8-19
control register 8-16
extensions 8-2
hardware extensions 8-5
host 8-4
interface signals 8-2, 8-9
message transfer 8-21
Multi-ICE 8-3
request 8-13
signals A-8
state 8-2
status register 8-16
support 8-16
systems 8-4
Debug state
actions of ARM9E-S 8-13
breakpoints 8-9
watchpoints 8-11
Disabling EmbeddedICE-RT 8-18
DMA
interface 5-1
Index-2
DMAA A-15
DMAD A-15
DMAENABLE A-15
DMAMAS A-15
DMAnREQ A-15
DMAnRW A-15
DMARData A-15
DMAReady A-15
DMAWait A-15
Drain write buffer 2-8
D-SRAM 3-3
E
EDBGRQ 8-18, A-9
EmbeddedICE-RT 8-5, 8-13
debug communications channel
8-19
debug status register 8-15
disabling 8-18
macrocell 8-16
operation 8-16
overview 8-16
Endian bit 2-7
ETM interface signals A-12
ETMBIGEND A-12
ETMCHSD A-13
ETMCHSE A-13
ETMDA A-12
ETMDABORT A-12
ETMDBGACK A-12
ETMDMAS A-12
ETMDMORE A-12
ETMDnMREQ A-12
ETMDnRW A-12
ETMDSEQ A-12
ETMEN A-12
ETMHIVECS A-12
ETMIA A-12
ETMID15TO8 A-13
ETMID31TO24 A-13
ETMInMREQ A-12
ETMINSTREXEC A-12
ETMISEQ A-12
ETMITBIT A-12
ETMLATECANCEL A-13
ETMnWAIT A-12
ETMPASS A-13
Copyright © 2000 ARM Limited. All rights reserved.
ETMRDATA A-12
ETMRNGOUT A-12
ETMWDATA A-12
Exception vectors 2-6
F
FIFOFULL A-12
H
HADDR A-4
HBURST A-4
HBUSREQ A-5
HCLKEN A-3
HGRANT A-5
HLOCK A-5
HPROT A-4
HRDATA A-4
HREADY A-4
HRESETn A-3
HRESP A-4
HSIZE A-4
HTRANS A-4
HWDATA A-4
HWRITE A-4
I
ICAPTUREEN A-14
ID code register 2-5
INITRAM A-11
Instruction SRAM 3-3
INTEST wrapper signals A-14
I-SRAM 3-3
J
JTAG interface 8-2, 8-5
L
Low-power mode 2-8
ARM DDI 0186A