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Instruction cycle timings
AHB access
Back-to-back
,
LDR/LDR
,
,
LDR/STR
STR/STR
STR/LDR
Simultaneous
LDR/STR
and
instruction fetch
of n words
STM
of n words, simultaneous
STM
instruction fetch at end
of n words crosses 1KB
STM
region
LDM
of n words
LDM
of n words, simultaneous
instruction fetch at end
of n words crosses 1KB
LDM
region
11-8
Table 11-4 AHB read and unbuffered write transfer cycles (continued)
Cycles
Sync+2(N+I)
Sync+2N+I
Sync+N+(n-1)S+I
Sync+2N+(n-1)S+I
Sync+2N+(n-2)S+2I
Sync+N+(n-1)S+2I
Sync+2N+(n-1)S+2I
Sync+2N+(n-2)S+4I
See AHB bus master interface on page 6-7 for diagrams of the cycles listed in
Table 11-4 on page 11-7.
Table 11-5 on page 11-9 shows the cycles required to perform buffered writes. These
writes usually take place in parallel with program execution and the ARM9E-S core is
not stalled while the buffered writes take place. However, whenever a load or instruction
fetch to the AHB is required, the core is stalled and the write buffer drained before
program execution can continue.
Copyright © 2000 ARM Limited. All rights reserved.
Comment
Assumes no AHB instruction fetch.
Synchronization penalty for first transfer only.
Optimization replaces IDLE cycle after
load/store with NONSEQ of instruction fetch.
Assumes no AHB instruction fetch.
Optimization replaces IDLE cycle after final
stored word with NONSEQ of instruction fetch.
Assumes no AHB instruction fetch,
sequentiality broken on boundary.
Assumes no AHB instruction fetch. LDM
requires extra IDLE at end of transfer to
re-sample core interface.
Optimization replaces second IDLE cycle after
final loaded word with NONSEQ of instruction
fetch.
Assumes no AHB instruction fetch,
sequentiality broken on boundary.
ARM DDI 0186A
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