Bufferable Write Address Space - ARM ARM966E-S Technical Reference Manual

Memory Map
3.3

Bufferable write address space

3-4
The use of the ARM966E-S write buffer is controlled by both the CP15 control register
and the fixed address map.
When the ARM966E-S comes out of reset, the write buffer is disabled by default. All
data writes to the AHB are performed as unbuffered. The ARM9E-S is stalled until the
BIU has performed the write on the AHB interface.
When the write buffer is enabled by writing to CP15 control register bit 3 (see
ARM966E-S CP15 registers on page 2-4), the data address (DA[31:0]) from the
ARM9E-S core controls whether the write buffer is used. If bit 28 of DA is set, the write
is treated as un-buffered. If bit 28 is clear however, the write is treated as a buffered write
and the BIU write buffer FIFO is used. Buffered writes allow the core to continue
program execution while the write is performed on the AHB. If the write buffer is full
the core is stalled until space becomes available in the FIFO. See Write buffer operation
on page 6-3 for details of the BIU and write buffer behavior.
Note
Writes to tightly-coupled SRAM address space do not get sent to the AHB if the SRAM
being accessed is enabled (the SRAMs do not write-through). If either SRAM is
disabled and a write is performed to its address space, the write is performed as a
buffered AHB write if the write buffer is enabled. If not, the write is un-buffered.
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