Figure 6-14 Arm966E-S Clk To Ahb Hclk Sampling - ARM ARM966E-S Technical Reference Manual

ARM DDI 0186A
In this example, the slave peripheral has an input setup and hold, and an output hold and
valid time relative to HCLK. The ARM966E-S has an input setup and hold, and an
output hold and valid relative to CLK', the clock at the bottom of the clock tree. Clock
tree insertion must be used to position the HCLK to match CLK' for optimal
performance.
Hierarchical clock tree insertion
If the ARM966E-S has clock tree insertion performed before embedding it, buffers are
added on input data to match the clock tree so that the setup and hold is relative to the
top level CLK. This is guaranteed to be safe at the expense of extra buffers in the data
input path.
The HCLK domain AHB peripherals must still meet the ARM966E-S input setup and
hold requirements. Because the ARM966E-S inputs and outputs are now relative to
CLK, the outputs do appear comparatively later by the value of the insertion delay. This
ultimately leads to lower AHB performance.
Copyright © 2000 ARM Limited. All rights reserved.
CLK
Clock tree
÷
HCLKEN
N
HCLK

Figure 6-14 ARM966E-S CLK to AHB HCLK sampling

Bus Interface Unit
ARM966E-S
CLK'
HRDATA[31:0]
AHB slave mux
AHB
HADDR[31:0]
slave
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