ARM ARM966E-S Technical Reference Manual page 187

Index
A
AHB signals A-4
ARM instruction set 1-2
ARM9E-S memory map 3-2
ARM966E-S 1-2
B
Base restored data abort model 2-3
Base updated data abort model 2-3
BIGENDOUT A-11
BIST
control register 2-10
size encoding 2-11
Block diagram 1-3
Breakpoints 8-9, 8-17
exceptions 8-10
instruction boundary 8-10
Prefetch Abort 8-10
timing 8-10
Bufferable write address space 3-4
ARM DDI 0186A
Busy-wait 7-5
abandoned 7-12
interrupted 7-12
C
CHSDE A-6
CHSEX A-6
CLK A-3
Clock
domains 8-14
interface signals A-3
system 8-3
test 8-3
COMMRX A-8
COMMTX A-9
Control register 2-5
Conventions
typographical xiii
Coprocessor
handshake signals 7-5
handshake states 7-5
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instruction, busy-wait 7-5
interface signals A-6
Core control register 2-7
Core state, determining 8-15
CPCLKEN A-6
CPDIN A-6
CPDOUT A-6
CPINSTR A-6
CPLATECANCEL 7-5, A-6
CPPASS A-6
CPTBIT A-7
CP14 2-2
CP15 2-2
registers 2-4
D
Data Abort model 2-3
Data SRAM 3-3
enable 2-7
DBGACK 8-9, 8-18, A-9
DBGDEWPT 8-18, A-10
Index-1