Tightly-Coupled Sram Address Space; Figure 3-2 I-Sram Aliasing Example - ARM ARM966E-S Technical Reference Manual

3.2

Tightly-coupled SRAM address space

ARM DDI 0186A
The tightly-coupled Instruction SRAM (I-SRAM) and Data SRAM (D-SRAM) are
located at the bottom of the memory map. Each SRAM is allocated a 64MB address
space, the bottom 64MB space mapping to I-SRAM and the next 64MB range mapping
to D-SRAM.
In practice, each SRAM is likely to be much smaller than the 64MB allowable and the
address decode is implemented so that each memory is aliased throughout its 64MB
range. See Figure 3-2 for an example of a 16KB I-SRAM aliased through the 64MB
address space.
All accesses to addresses above the 128MB combined SRAM address space result in
AMBA AHB transfers controlled by the Bus Interface Unit (BIU).
An instruction fetch from the ARM9E-S core to the D-SRAM address space goes to the
AHB, regardless of whether the D-SRAM is enabled. A data interface access from the
ARM9E-S core can access both the D-SRAM and the I-SRAM. The ability to
additionally access the I-SRAM is required to allow the fetching of inline literals within
code, for programming of the instruction I-SRAM, and for debugging purposes.
When an SRAM is disabled, all accesses to its address space go to the AHB. When
enabled, the SRAM must be programmed before use. The tightly-coupled SRAMs can
be enabled or disabled during reset depending on the value of the input pin INITRAM.
Several boot options are available using INITRAM and the exception vectors location
pin VINITHI. These are discussed in Using INITRAM input pin on page 4-4.
Copyright © 2000 ARM Limited. All rights reserved.
D-SRAM space
0x0400 0000
0x03FF FFFF
I-SRAM alias #4095
0x03FF C000
0x0000 BFFF
I-SRAM alias #2
0x0000 8000
0x0000 7FFF
I-SRAM alias #1
0x0000 4000
0x0000 3FFF
I-SRAM (16KB)
0x0000 0000

Figure 3-2 I-SRAM aliasing example

Memory Map
3-3