ARM ARM966E-S Technical Reference Manual page 180

SRAM Stall Cycles
C-4
It is possible for the ARM9E-S to issue a simultaneous instruction and data request, and
if the data request addresses the I-SRAM, a stall cycle is required (see Figure C-3).
I-SRAM Addr
RDATA[31:0]
INSTR[31:0]
SYSCLKEN
Note
In the case of simultaneous I-SRAM and D-SRAM read access requests from the
ARM9E-S core, the instruction fetch is always performed first, followed by the data
read. The core is disabled until both accesses have completed.
Data read
To maximize the I-SRAM interface frequency performance, data read requests to this
RAM are pipelined. This adds a stall cycle for every data read instruction. An example
of a data read from the I-SRAM is shown in on page C-5.
Copyright © 2000 ARM Limited. All rights reserved.
CLK
DnMREQ
InMREQ
DnRW
Addr A (read)
DA[31:1]
Addr B (I fetch)
IA[31:1]
Addr A
Figure C-3 Simultaneous instruction fetch, data read
inst. fetch
data read
stall
cycle
Addr B
Read data (A)
Read Instr (B)
ARM DDI 0186A