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Test Support
The programmer can poll the BIST control register to detect when a test has paused (the
running flag is LOW). Data can then be corrupted as detailed above, before restarting
the BIST test.
User pause
If the pause bit is clear when the test is activated, the test is run in user pause mode. The
BIST algorithm is paused by an MCR to the BIST control register, setting the pause bit
for the SRAM being tested. The SRAM contents are then corrupted as previously. This
stops the BIST algorithm at a potentially unknown point, resulting in the possibility that
the corrupted data is overwritten by the BIST algorithm and therefore not cause a test
to fail.
Note
User pause mode is provided for production test debugging to shorten a test by pausing
the algorithm early. The auto pause mechanism is recommended to provide or BIST
hardware testing for all other occasions.
ARM DDI 0186A
Copyright © 2000 ARM Limited. All rights reserved.
10-7
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