I-Sram Data Write Followed By Instruction Fetch - ARM ARM966E-S Technical Reference Manual

ARM DDI 0186A
CLK
DnMREQ
InMREQ
DnRW
DA[31:1]
IA[31:1]
I-SRAM Addr
WDATA[31:0]
INSTR[31:0]
SYSCLKEN

I-SRAM data write followed by instruction fetch

This class of stall occurs when a data write to the I-SRAM address space is performed,
followed by an instruction fetch request in the next cycle. It is similar to the generic read
follows write scenario of each SRAM except that the read is an instruction fetch rather
than a data load. The instruction fetch must be held off until the write has completed,
requiring that the ARM9E-S core is stalled for a cycle (see Figure C-7 on page C-8).
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I-SRAM
data write
stall
cycle
Addr A (write)
Addr B (I fetch)
Addr A
Write data (A)
Figure C-6 Simultaneous instruction fetch, data write
SRAM Stall Cycles
I-SRAM
inst. fetch
stall
cycle
Addr B
Read Instr (B)
C-7